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331 records (took 0.052 seconds)

    Display device
    91.
    发明授权
    Display device 有权

    公开(公告)号：US10134775B2

    公开(公告)日：2018-11-20

    申请号：US15899472

    申请日：2018-02-20

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Atsushi Umezaki

    IPC: G09G3/36 ,  H01L27/12 ,  G11C19/28 ,  H01L27/105 ,  G02F1/1333 ,  G02F1/1368 ,  G09G3/3266 ,  G02F1/1362 ,  H01L29/423 ,  H01L29/786 ,  H01L27/13 ,  G02F1/1343 ,  G02F1/1345 ,  H01L27/32

    Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

    Semiconductor device
    94.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09990894B2

    公开(公告)日：2018-06-05

    申请号：US15396862

    申请日：2017-01-03

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hajime Kimura ,  Atsushi Umezaki

    IPC: G09G5/00 ,  G09G3/36

    CPC classification number: G09G3/3648 ,  G09G3/2096 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2320/0209 ,  G09G2320/0223 ,  G09G2320/043

    Abstract: A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

    Semiconductor device
    99.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09608010B2

    公开(公告)日：2017-03-28

    申请号：US14713941

    申请日：2015-05-15

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Atsushi Umezaki

    IPC: G11C19/00 ,  H01L27/12 ,  G11C19/28 ,  H01L27/088 ,  H01L27/15 ,  H01L27/32

    CPC classification number: G11C19/28 ,  G09G3/2092 ,  G09G2310/0267 ,  G09G2310/0286 ,  H01L27/088 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/156 ,  H01L27/3244 ,  H01L29/7869

    Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

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