利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

117 条记录 (耗时 0.04 秒)

    Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene process
    91.
    发明授权
    Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene process 有权
    用于减少在双镶嵌工艺中产生的无边界通孔的微切削的方法和装置

    公开(公告)号：US06794304B1

    公开(公告)日：2004-09-21

    申请号：US10631528

    申请日：2003-07-31

    申请人： Shiqun Gu ,  Masaichi Eda ,  Peter McGrath ,  Hong Lin ,  Jim Elmer

    发明人： Shiqun Gu ,  Masaichi Eda ,  Peter McGrath ,  Hong Lin ,  Jim Elmer

    IPC分类号： H01L21302

    CPC分类号： H01L21/76897 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76834

    摘要： A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially non-electrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. The first layer has a thickness in the vertical direction that is greater in an area over the downward slope of the second element than in an area over the first element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated in the vertically thicker area above the downwardly sloping upper surface of the second element.

    摘要翻译： 制造半导体器件的方法包括提供由第一基本上导电的材料形成并具有上表面的第一元件。 提供了与第一元件相邻的第二元件。 第二元件由第一基本上不导电的材料形成。 第二元件的上表面朝向第一元件的上表面向下倾斜。 第二基本上非导电材料的第一层设置在第一元件的上表面和第二元件的上表面之上。 第一层具有在垂直方向上的厚度，该厚度在第二元件的向下倾斜度上比在第一元件上的区域中大得多。 进行蚀刻处理，使得该层在第一元件的上表面上方穿孔，并且在第二元件的向下倾斜的上表面上方的垂直较厚的区域中无孔。

    Optical intensity modifier
    92.
    发明授权
    Optical intensity modifier 有权
    光强度调节剂

    公开(公告)号：US06498045B1

    公开(公告)日：2002-12-24

    申请号：US09878741

    申请日：2001-06-11

    申请人： Shiqun Gu

    发明人： Shiqun Gu

    IPC分类号： H01L2100

    CPC分类号： H01J37/32935 ,  H01J37/32963 ,  H01J37/32972

    摘要： A method for detecting an end point of an etching step conducted in an etching chamber. A target emission intensity level is selected for the etching step, and the etching step is performed in the etching chamber. A raw emission intensity level is sensed from the etching chamber during the etching step with an emission intensity level detector. The raw emission intensity level sensed from the etching chamber by the emission detector is modified with an emission intensity level modifier. The raw emission intensity level sensed with the emission intensity level detector from the etching chamber during the etching step is adjusted to the target emission intensity level by adjusting the emission intensity level modifier. The etching process is stopped upon occurrence of a predetermined spectral event sensed by the emission intensity level detector.

    摘要翻译： 一种用于检测在蚀刻室中进行的蚀刻步骤的终点的方法。 对于蚀刻步骤选择目标发光强度水平，并且在蚀刻室中进行蚀刻步骤。 在蚀刻步骤期间利用发射强度电平检测器从蚀刻室检测原始发射强度水平。 通过发射检测器从蚀刻室检测的原始发射强度水平用发射强度水平调节剂修改。 通过调整发光强度水平调节器，将在蚀刻步骤期间从蚀刻室的发射强度水平检测器感测的原始发光强度水平调整为目标发光强度水平。 当发生由发射强度电平检测器感测到的预定光谱事件时，蚀刻处理停止。

    Low-K dielectric protection spacer for patterning through substrate vias through a low-K wiring layer
    93.
    发明授权
    Low-K dielectric protection spacer for patterning through substrate vias through a low-K wiring layer 有权
    低K介质保护隔离物，用于通过低K布线层的衬底通孔进行图案化

    公开(公告)号：US09059263B2

    公开(公告)日：2015-06-16

    申请号：US13588438

    申请日：2012-08-17

    申请人： Vidhya Ramachandran ,  Shiqun Gu

    发明人： Vidhya Ramachandran ,  Shiqun Gu

    IPC分类号： H01L21/338 ,  H01L21/768 ,  H01L23/48

    CPC分类号： H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A low-K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low-K value wiring layer. A method for forming a low-K value dielectric protection spacer includes etching a via opening through a low-K value dielectric interconnect layer. A protective layer is deposited in the via opening and on the low-K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low-K value dielectric interconnect layer. The etching leaving a protective sidewall spacer on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material.

    摘要翻译： 低K值介电保护间隔物，用于通过低K值布线层通过衬底通孔（TSV）进行构图。 形成低K值介电保护间隔物的方法包括通过低K值电介质互连层蚀刻通孔。 保护层沉积在通孔开口和低K值电介质互连层上。 保护层的至少一部分从通孔开口的底部和低K值电介质互连层的水平表面被蚀刻。 蚀刻在通孔开口的侧壁上留下保护性侧壁间隔物。 穿通基板通孔被蚀刻穿过通孔开口的底部并穿过半导体基板。 直通基板通孔用导电材料填充。

    Low cost die-to-wafer alignment/bond for 3d IC stacking
    95.
    发明授权
    Low cost die-to-wafer alignment/bond for 3d IC stacking 有权
    3d IC堆叠的低成本芯片对晶圆对准/焊接

    公开(公告)号：US08796073B2

    公开(公告)日：2014-08-05

    申请号：US12236967

    申请日：2008-09-24

    申请人： Shiqun Gu ,  Thomas R. Toms

    发明人： Shiqun Gu ,  Thomas R. Toms

    IPC分类号： H01L21/00

    CPC分类号： H01L23/544 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54406 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2223/5448 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

    摘要： The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.

    摘要翻译： 在对准步骤期间，可以通过对准多个管芯而不是单个管芯来降低与叠置的IC器件中的对准相关的成本。 在一个实施例中，对准结构被放置在划线中，而不是在模具本身内。 对准四个模具而不是一个消除了对于多个对准指示器的需要，因此在晶片上更多的硅可用于有源区域。 此外，该方法允许通过对具有相同产量构型的模具进行分级来提高产量。

    Voltage switchable dielectric for die-level electrostatic discharge (ESD) protection
    96.
    发明授权
    Voltage switchable dielectric for die-level electrostatic discharge (ESD) protection 有权
    用于芯片级静电放电（ESD）保护的电压可切换电介质

    公开(公告)号：US08633562B2

    公开(公告)日：2014-01-21

    申请号：US13078672

    申请日：2011-04-01

    申请人： Shiqun Gu ,  Ratibor Radojcic ,  Yiming Li

    发明人： Shiqun Gu ,  Ratibor Radojcic ,  Yiming Li

    IPC分类号： H01L23/58

    CPC分类号： H01L23/62 ,  H01L23/29 ,  H01L23/60 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

    摘要： A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.

    摘要翻译： 可以在用于静电放电（ESD）保护的管芯上使用电压可切换电介质层。 电压切换介电层在芯片的正常操作期间用作模具的端子之间的介电层。 当在芯片的端子处发生ESD事件时，端子之间的高电压将可切换电压的电介质层切换成导电层，以允许电流放电到裸片的接地端子，而不会流过电流通过电路的电路。 因此，在具有可电压切换介电层的管芯上的ESD事件期间，对管芯电路的损坏被减小或防止。 电压可切换电介质层可以沉积在管芯的背面上，用于在与第二管芯堆叠期间进行保护以形成堆叠的IC。

    Corrosion control of stacked integrated circuits
    97.
    发明授权
    Corrosion control of stacked integrated circuits 有权
    堆叠式集成电路的腐蚀控制

    公开(公告)号：US08618670B2

    公开(公告)日：2013-12-31

    申请号：US12192514

    申请日：2008-08-15

    申请人： Shiqun Gu ,  Matthew Nowak

    发明人： Shiqun Gu ,  Matthew Nowak

    IPC分类号： H01L23/20 ,  H01L21/58

    CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    摘要： A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity.

    摘要翻译： 一种系统和方法可以防止腐蚀性元件（或至少氧化剂）在层叠IC器件的两层之间的界面处与金属连接接触。 当层彼此靠近地定位时，在层的平面表面的边界处形成空腔。 该空腔由层之间的周边密封界定。 在一个实施例中，在空腔内产生真空，从而减小空腔内的腐蚀性气氛。 在另一个实施例中，空腔填充惰性气体，例如氩气。 一旦腔体的氧化元件减少，外围密封件就可以被密封，以防止污染物进入腔体中。

    Predictive modeling of interconnect modules for advanced on-chip interconnect technology
    99.
    发明授权
    Predictive modeling of interconnect modules for advanced on-chip interconnect technology 失效
    用于先进片上互连技术的互连模块的预测建模

    公开(公告)号：US08429577B2

    公开(公告)日：2013-04-23

    申请号：US12474297

    申请日：2009-05-29

    申请人： Xia Li ,  Wei Zhao ,  Yu Cao ,  Shiqun Gu ,  Seung H. Kang ,  Matthew Nowak

    发明人： Xia Li ,  Wei Zhao ,  Yu Cao ,  Shiqun Gu ,  Seung H. Kang ,  Matthew Nowak

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5036

    摘要： A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.

    摘要翻译： 计算机程序产品估计半导体集成电路（IC）的互连结构的性能。 程序产品包括在计算机上执行的代码，用于基于考虑到互连结构的多层的输入数据来计算互连结构的至少一个电特性。 电气特性可以是电容，电阻和/或电感。 电容可以基于多个分量，包括边缘电容分量，端子电容分量和耦合电容分量。