公开(公告)号：US11726539B2

公开(公告)日：2023-08-15

申请号：US17410938

申请日：2021-08-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Chen Kuo ,  Yangsyu Lin ,  Yu-Hao Hsu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G06F1/32 ,  G06F1/3206 ,  G06F1/3234

CPC分类号： G06F1/3206 ,  G06F1/3275

摘要： A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal according to a first power supply signal from a first power supply and a status signal. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal, according to the first power management signal and the status signal.

公开(公告)号：US11714570B2

公开(公告)日：2023-08-01

申请号：US17130918

申请日：2020-12-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jonathan Tsung-Yung Chang ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Yen-Huei Chen ,  Yih Wang ,  Haruki Mori

IPC分类号： G06F3/06 ,  G11C11/419 ,  G11C7/10 ,  G11C8/16 ,  G06N3/063

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0673 ,  G06N3/063 ,  G11C7/10 ,  G11C8/16 ,  G11C11/419

摘要： A charge sharing scheme is used to mitigate the variations in cell currents in order to achieve higher accuracy for CIM computing. In some embodiments, a capacitor is associated with each SRAM cell, and the capacitors associated with all SRAM cells in a column are included in averaging the RBL current. In some embodiments, a memory unit associated to an RBL in a CIM device includes a storage element adapted to store a weight, a first switch device connected to the storage element and adapted to be controlled by an input signal and generate a product signal having a magnitude indicative of the product of the input signal and the stored weight. The memory unit further includes a capacitor adapted to receive the product signal and store an amount of charge corresponding to the magnitude of the product signal. The memory unit further include a second switch device adapted to transfer the charge on the capacitor to the RBL.

公开(公告)号：US20230185324A1

公开(公告)日：2023-06-15

申请号：US18165093

申请日：2023-02-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Haruki Mori ,  Hidehiro Fujiwara ,  Zhi-Hao Chang ,  Yangsyu Lin ,  Yu-Hao Hsu ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Chiting Cheng

IPC分类号： G05F3/24 ,  G06F1/28 ,  H01L27/092 ,  H01L23/528 ,  G05F1/10

CPC分类号： G05F3/24 ,  G06F1/28 ,  H01L27/092 ,  H01L23/5286 ,  G05F1/10

摘要： Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

公开(公告)号：US11670362B2

公开(公告)日：2023-06-06

申请号：US17687272

申请日：2022-03-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao

IPC分类号： G11C11/40 ,  G11C11/408 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093

CPC分类号： G11C11/4085 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4093

摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

公开(公告)号：US11651804B2

公开(公告)日：2023-05-16

申请号：US17335866

申请日：2021-06-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-Kuo Su ,  Chiting Cheng ,  Pankaj Aggarwal ,  Yen-Huei Chen ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Jhon Jhy Liaw

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C11/419

CPC分类号： G11C7/12 ,  G11C7/227 ,  G11C11/419

摘要： A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first memory cell array includes rows of memory cells and columns of memory cells. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line coupled to the first and second set of memory cells. The first set of pull-down cells or loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and configured to charge the first tracking bit line to a pre-charge voltage level responsive to a tracking enable signal.

公开(公告)号：US11610628B2

公开(公告)日：2023-03-21

申请号：US17334083

申请日：2021-05-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng Wu ,  Hung-Jen Liao ,  Ping-Wei Wang ,  Wei Min Chan ,  Yen-Huei Chen

IPC分类号： G11C11/41 ,  G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/412

摘要： A static random access memory (SRAM) includes a bit cell including a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a read multiplexer connected to the bit information path. The read multiplexer includes an n-type transistor configured to selectively couple the bit information path to a sense amplifier.

公开(公告)号：US20220367337A1

公开(公告)日：2022-11-17

申请号：US17816108

申请日：2022-07-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Yuan Chen ,  Cheng-Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh ,  Kao-Cheng Lin ,  Wei-Min Chan

IPC分类号： H01L23/528 ,  H01L27/11 ,  H01L27/092 ,  G06F30/392 ,  H01L21/8238

摘要： Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

公开(公告)号：US11468929B2

公开(公告)日：2022-10-11

申请号：US17235297

申请日：2021-04-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao ,  Fu-An Wu ,  He-Zhou Wan ,  XiuLi Yang

IPC分类号： G11C16/10 ,  G11C7/22 ,  G11C7/12 ,  G11C7/14 ,  G11C7/10

摘要： A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

公开(公告)号：US11444608B2

公开(公告)日：2022-09-13

申请号：US17366592

申请日：2021-07-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Yuan Chen ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh

IPC分类号： H03K3/356 ,  H03K19/0185 ,  H03K17/687 ,  G11C11/56

摘要： A level shifter includes: a first inverter configured to receive an input signal in a low voltage domain and shift the input signal from the low voltage domain to a first output signal at a first output terminal in a high voltage domain higher than the low voltage domain in response to a logical high state of a first clock signal in the low voltage domain; a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the low voltage domain to a second output signal at a second output terminal in the high voltage domain in response to the logical high state; a first NMOS sensing transistor and a second NMOS sensing transistor; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal.

公开(公告)号：US20220254712A1

公开(公告)日：2022-08-11

申请号：US17173750

申请日：2021-02-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Yuan Chen ,  Cheng-Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh ,  Kao-Cheng Lin ,  Wei-Min Chan

IPC分类号： H01L23/528 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  G06F30/392

摘要： Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.