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    Semiconductor device with tunable work function
    91.
    发明授权
    Semiconductor device with tunable work function 有权
    具有可调功能的半导体器件

    公开(公告)号：US09548372B2

    公开(公告)日：2017-01-17

    申请号：US14609138

    申请日：2015-01-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Wei Zhang

    IPC: H01L29/51 ,  H01L29/423

    CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

    Abstract: The metal-oxide semiconductor structure includes a substrate, a gate dielectric multi-layer, an etch stop layer, a work function metallic layer, a barrier layer and a silicide layer. The substrate has a trench. The gate dielectric multi-layer overlies the trench, in which the gate dielectric multi-layer includes a high-k capping layer with a fluorine concentration substantially in a range from 1 at % to 10 at %. The etch stop layer is disposed on the gate dielectric multi-layer. The work function metallic layer is disposed on the etch stop layer. The barrier layer is disposed on the work function metallic layer. The silicide layer is disposed on the barrier layer.

    Abstract translation: 金属氧化物半导体结构包括衬底，栅极电介质多层，蚀刻停止层，功函数金属层，阻挡层和硅化物层。 衬底具有沟槽。 栅极电介质多层覆盖沟槽，其中栅极电介质多层包括氟浓度基本上在1at％至10at％范围内的高k覆盖层。 蚀刻停止层设置在栅极电介质多层上。 功函数金属层设置在蚀刻停止层上。 阻挡层设置在功函数金属层上。 硅化物层设置在阻挡层上。

    Barrier layer for metal insulator metal capacitors
    92.
    发明授权
    Barrier layer for metal insulator metal capacitors 有权

    公开(公告)号：US12211890B2

    公开(公告)日：2025-01-28

    申请号：US17815524

    申请日：2022-07-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Anhao Cheng ,  Fang-Ting Kuo ,  Yen-Yu Chen

    IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02

    Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

    Gate structures for tuning threshold voltage
    93.
    发明授权
    Gate structures for tuning threshold voltage 有权

    公开(公告)号：US12205850B2

    公开(公告)日：2025-01-21

    申请号：US17810799

    申请日：2022-07-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

    IPC: H01L21/8238 ,  H01L21/033 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78

    Abstract: A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.

    Integrated circuits with doped gate dielectrics
    100.
    发明授权
    Integrated circuits with doped gate dielectrics 有权

    公开(公告)号：US11605537B2

    公开(公告)日：2023-03-14

    申请号：US17181970

    申请日：2021-02-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Yen-Yu Chen

    IPC: H01L29/78 ,  H01L21/32 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49

    Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

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