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    Semiconductor structure and integrated circuit
    95.
    发明授权
    Semiconductor structure and integrated circuit 有权
    半导体结构和集成电路

    公开(公告)号：US08981488B1

    公开(公告)日：2015-03-17

    申请号：US14072976

    申请日：2013-11-06

    Applicant: United Microelectronics Corp.

    Inventor： Yung-Ju Wen ,  Tien-Hao Tang ,  Chang-Tzu Wang

    IPC: H01L21/70 ,  H01L27/092

    CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L21/823493

    Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes a first field-effect transistor (FET), a second FET, an isolation structure, and a body electrode. The first FET includes a first active body having a first type conductivity. The second FET includes a second active body having the first type conductivity. The first active body and the second active body are isolated from each other by the isolation structure. The body electrode has the first type conductivity and formed in the second active body.

    Abstract translation: 提供半导体结构和集成电路。 半导体结构包括第一场效应晶体管（FET），第二FET，隔离结构和体电极。 第一FET包括具有第一类型导电性的第一有源体。 第二FET包括具有第一类型导电性的第二有源体。 第一活性体和第二活性体通过隔离结构彼此隔离。 主体电极具有第一类型的导电性并且形成在第二主动体中。

    Output buffer
    96.
    发明授权
    Output buffer 有权
    输出缓冲区

    公开(公告)号：US08884337B2

    公开(公告)日：2014-11-11

    申请号：US13858927

    申请日：2013-04-08

    Applicant: United Microelectronics Corp.

    Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang

    IPC: H01L27/118 ,  H03K3/013

    CPC classification number: H03K19/00 ,  H01L27/0207 ,  H01L27/0738 ,  H01L27/088 ,  H01L27/092 ,  H03K19/00361

    Abstract: An output buffer includes an input/output end, a voltage source, a first transistor and a second transistor. The first transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The second transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The control end of the first transistor and the control end of the second transistor are substantially perpendicular to each other, and the punch through voltage of the first transistor is higher than the punch through voltage of the second transistor.

    Abstract translation: 输出缓冲器包括输入/​​输出端，电压源，第一晶体管和第二晶体管。 第一晶体管包括耦合到输入/输出端的第一端，耦合到电压源的第二端和耦合到电压源的控制端。 第二晶体管包括耦合到输入/输出端的第一端，耦合到电压源的第二端和耦合到电压源的控制端。 第一晶体管的控制端和第二晶体管的控制端基本上彼此垂直，并且第一晶体管的穿通电压高于第二晶体管的穿通电压。

    SEMICONDUCTOR DEVICE
    97.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140319613A1

    公开(公告)日：2014-10-30

    申请号：US13873261

    申请日：2013-04-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Ning He ,  Lu-An Chen ,  Tien-Hao Tang

    IPC: H01L23/552

    CPC classification number: H01L27/0248 ,  H01L27/0266 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7816

    Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain and a source formed in the substrate at respective two sides of the gate, and a doped region formed in the source. The drain and the source comprise a first conductivity type and the doped region comprises a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

    Abstract translation: 半导体器件包括衬底，位于衬底上的栅极，在栅极的相应两侧在衬底中形成的漏极和源极以及形成在源极中的掺杂区域。 漏极和源极包括第一导电类型，并且掺杂区域包括第二导电类型。 第一导电类型和第二导电类型彼此互补。

    ESD protection circuit and ESD protection device thereof
    98.
    发明授权
    ESD protection circuit and ESD protection device thereof 有权
    ESD保护电路及其ESD保护装置

    公开(公告)号：US08711535B2

    公开(公告)日：2014-04-29

    申请号：US13891199

    申请日：2013-05-10

    Applicant: United Microelectronics Corp.

    Inventor： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H02H3/20 ,  H01L27/02

    CPC classification number: H02H3/20 ,  H01L27/0262 ,  H01L2924/1301 ,  H01L2924/1304 ,  H02H9/04 ,  H02H9/046

    Abstract: The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

    Abstract translation: ESD保护电路电连接在第一电力轨道和第二电力轨道之间，并且包括ESD保护装置，电连接在ESD保护装置和第一电力轨道之间的开关装置和电连接在第一电力轨道之间的低通滤波器 第一电力轨道和第一开关装置。 ESD保护器件包括BJT和电连接在BJT的基极和第一电源轨之间的第一电阻器。 当不发生ESD事件时，基极的电位大于或等于BJT发射极的电位。 当ESD事件发生时，基极的电位小于发射极的电位。

    ESD protection circuit and ESD protection device thereof
    99.
    发明申请
    ESD protection circuit and ESD protection device thereof 有权
    ESD保护电路及其ESD保护装置

    公开(公告)号：US20130250462A1

    公开(公告)日：2013-09-26

    申请号：US13891199

    申请日：2013-05-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H02H9/04

    CPC classification number: H02H3/20 ,  H01L27/0262 ,  H01L2924/1301 ,  H01L2924/1304 ,  H02H9/04 ,  H02H9/046

    Abstract: The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

    Abstract translation: ESD保护电路电连接在第一电力轨道和第二电力轨道之间，并且包括ESD保护装置，电连接在ESD保护装置和第一电力轨道之间的开关装置和电连接在第一电力轨道之间的低通滤波器 第一电力轨道和第一开关装置。 ESD保护器件包括BJT和电连接在BJT的基极和第一电源轨之间的第一电阻器。 当不发生ESD事件时，基极的电位大于或等于BJT发射极的电位。 当ESD事件发生时，基极的电位小于发射极的电位。

    ELECTROSTATIC DISCHARGE PROTECTION DEVICE
    100.
    发明公开
    ELECTROSTATIC DISCHARGE PROTECTION DEVICE 审中-公开

    公开(公告)号：US20230299158A1

    公开(公告)日：2023-09-21

    申请号：US17719351

    申请日：2022-04-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuan-Yu Lu ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H01L29/417 ,  H01L23/522 ,  H01L27/02

    CPC classification number: H01L29/41775 ,  H01L23/5226 ,  H01L27/0266 ,  H01L29/7835

    Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a gate structure, a source doped region, a drain doped region, source silicide patterns, and drain silicide patterns. The gate structure is disposed on the semiconductor substrate. The source doped region and the drain doped region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction, respectively. The source silicide patterns are disposed on the source doped region. The source silicide patterns are arranged in a second direction and separated from one another. The drain silicide patterns are disposed on the drain doped region. The drain silicide patterns are arranged in the second direction and separated from one another. The source silicide patterns and the drain silicide patterns are arranged misaligned with one another in the first direction.

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