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141 条记录 (耗时 0.026 秒)

    Three-dimensional type inductor for mixed mode radio frequency device
    91.
    发明授权
    Three-dimensional type inductor for mixed mode radio frequency device 有权
    用于混合模式射频设备的三维型电感器

    公开(公告)号：US06291872B1

    公开(公告)日：2001-09-18

    申请号：US09433255

    申请日：1999-11-04

    申请人： Ying-Lang Wang ,  Hway-Chi Lin ,  Jun Wu ,  Jowei Dun

    发明人： Ying-Lang Wang ,  Hway-Chi Lin ,  Jun Wu ,  Jowei Dun

    IPC分类号： H01L2900

    CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01L27/08

    摘要： Vertical type structures for integrated circuit inductors are disclosed. These vertical type inductors include the single-loop type, the parallel-loop type and the screw type, which form three different embodiments in the present invention. In the first embodiment, three-dimensional type structures, a single-loop type is utilized as an integrated circuit inductor. This inductor structure is formed on a substrate and the axis of the structure is upright to the substrate. In another embodiment according to the present invention, a parallel-loop type structure for radio frequency (RF) integrated circuit inductor is provided. A screw type structure according to this invention is the third embodiment. It features an axis that is parallel to the surface of the substrate and threads into the semiconductor device.

    摘要翻译： 公开了集成电路电感器的垂直型结构。 这些垂直型电感器包括在本发明中形成三个不同实施例的单环型，并联环型和螺旋型。 在第一实施例中，采用单环型的三维型结构作为集成电路电感器。 该电感器结构形成在基板上，并且该结构的轴线垂直于基板。 在根据本发明的另一实施例中，提供了一种用于射频（RF）集成电路电感器的并联环路结构。 根据本发明的螺杆型结构是第三实施例。 它具有平行于衬底表面并进入半导体器件的轴线。

    Methods to improve copper-fluorinated silica glass interconnects
    93.
    发明授权
    Methods to improve copper-fluorinated silica glass interconnects 有权
    改善铜氟化石英玻璃互连的方法

    公开(公告)号：US6136680A

    公开(公告)日：2000-10-24

    申请号：US489498

    申请日：2000-01-21

    申请人： Jane-Bai Lai ,  Chung-Shi Liu ,  Tien-I Bao ,  Syun-Ming Jang ,  Chung-Long Chang ,  Hui-Ling Wang ,  Szu-An Wu ,  Wen-Kung Cheng ,  Chun-Ching Tsan ,  Ying-Lang Wang

    发明人： Jane-Bai Lai ,  Chung-Shi Liu ,  Tien-I Bao ,  Syun-Ming Jang ,  Chung-Long Chang ,  Hui-Ling Wang ,  Szu-An Wu ,  Wen-Kung Cheng ,  Chun-Ching Tsan ,  Ying-Lang Wang

    IPC分类号： H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76825 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/3212 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76883

    摘要： A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench. The FSG layer and planarized copper filled trench are then processed by either: (1) annealing from about 400 to 450.degree. C. for about one hour, then either NH.sub.3 or H.sub.2 plasma treating; or (2) Ar.sup.+ sputtering to ion implant Ar.sup.+ to a depth of less than about 300 .ANG. in the fluorinated silica glass layer, whereby any formed Si--OH bonds and copper oxide (metal oxide) are removed. A dielectric cap layer, having a predetermined thickness, is then formed over the processed FSG layer and the planarized copper filled trench.

    摘要翻译： 一种形成互连的方法，包括以下步骤。 提供一种半导体结构，其具有暴露的第一金属触点和形成在其上的电介质层。 然后在电介质层上形成具有预定厚度的FSG层。 具有预定宽度的沟槽形成在FSG层内，并且介电层露出第一金属接触。 具有预定厚度的阻挡层可以形成在FSG层之上并且衬在沟槽侧壁和底部。 然后将一种金属，优选铜沉积在阻挡层上，以形成具有预定厚度的铜层，超过所述阻挡层覆盖的FSG层，填充衬里的沟槽和覆盖填充阻挡层覆盖的FSG层的毯子。 所述FSG层的所述上表面上的铜层和阻挡层被平坦化，暴露出FSG层的上表面并形成平坦化的铜填充沟槽。 然后通过以下步骤之一处理FSG层和平坦化的铜填充沟槽：（1）从约400至450℃的退火约1小时，然后进行NH 3或H 2等离子体处理; 或者（2）在氟化石英玻璃层中，离子注入Ar +溅射至小于约300的深度，由此除去任何形成的Si-OH键和氧化铜（金属氧化物）。 然后在经处理的FSG层和平坦化的铜填充沟槽上形成具有预定厚度的电介质盖层。

    Methods and Apparatus for Resistive Random Access Memory (RRAM)
    96.
    发明申请
    Methods and Apparatus for Resistive Random Access Memory (RRAM) 有权
    电阻随机存取存储器（RRAM）的方法和装置

    公开(公告)号：US20130234094A1

    公开(公告)日：2013-09-12

    申请号：US13416183

    申请日：2012-03-09

    申请人： Ting-Chang Chang ,  Yong-En Syu ,  Fu-Yen Jian ,  Shih-Chieh Chang ,  Ying-Lang Wang

    发明人： Ting-Chang Chang ,  Yong-En Syu ,  Fu-Yen Jian ,  Shih-Chieh Chang ,  Ying-Lang Wang

    IPC分类号： H01L45/00

    CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/145 ,  H01L45/1608

    摘要： Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.

    摘要翻译： 公开了一种用于电阻随机存取存储器（RRAM）装置的方法和装置。 RRAM器件包括底电极，设置在底电极上的电阻开关层和设置在电阻开关层上的顶电极。 电阻开关层由金属，Si和O的复合材料制成。在顶部电极和底部电极之间可能存在额外的隧道势垒层。 顶部电极和底部电极可以包括多个子层。

    Method for forming IMD films
    97.
    发明授权
    Method for forming IMD films 有权
    形成IMD膜的方法

    公开(公告)号：US07253121B2

    公开(公告)日：2007-08-07

    申请号：US10937215

    申请日：2004-09-09

    申请人： Yi-Lung Cheng ,  Miao-Cheng Liao ,  Ying-Lang Wang

    发明人： Yi-Lung Cheng ,  Miao-Cheng Liao ,  Ying-Lang Wang

    IPC分类号： H01L21/471

    CPC分类号： H01L21/76807

    摘要： A method for forming IMD films. A substrate is provided. A plurality of dielectric films are formed on the substrate, wherein each of the dielectric layers are deposited in-situ in one chamber with only one thermal cycle.

    摘要翻译： 一种形成IMD膜的方法。 提供基板。 在基板上形成多个电介质膜，其中每个电介质层原位沉积在仅具有一个热循环的一个室中。

    Dual contact ring and method for metal ECP process
    98.
    发明授权
    Dual contact ring and method for metal ECP process 有权
    双接触环和金属ECP工艺方法

    公开(公告)号：US07252750B2

    公开(公告)日：2007-08-07

    申请号：US10664347

    申请日：2003-09-16

    申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Ke-Wei Chen ,  Ying-Lang Wang

    发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Ke-Wei Chen ,  Ying-Lang Wang

    IPC分类号： C25D17/00

    CPC分类号： C25D5/48 ,  C25D5/028 ,  Y10S204/07

    摘要： A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.

    摘要翻译： 用于接触晶片的图案化表面的双接触环和在晶片的图案化中心区域上的金属的电化学电镀，并从晶片的外边缘区域移除金属。 双接触环具有与晶片的外部边缘区域接触的外部电压环和与晶片的内部中心区域接触的内部电压环。 外部电压环连接到正电压源，内部电压环连接到负电压源。 内部电压环向晶片施加负电压以便于将金属电镀到晶片的图案化区域上。 通过外部电压环将正电压施加到晶片，以从衬底的外部边缘区域去除镀覆的金属。

    Damascene process using dielectic layer containing fluorine and nitrogen
    100.
    发明申请
    Damascene process using dielectic layer containing fluorine and nitrogen 审中-公开
    使用含氟和氮的介电层的镶嵌工艺

    公开(公告)号：US20060292859A1

    公开(公告)日：2006-12-28

    申请号：US11166237

    申请日：2005-06-27

    申请人： Shiu-Ko Jian ,  Sheng-Wen Chen ,  Hung-Jui Chang ,  Ying-Lang Wang

    发明人： Shiu-Ko Jian ,  Sheng-Wen Chen ,  Hung-Jui Chang ,  Ying-Lang Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/3144 ,  H01L21/31629

    摘要： An improved damascene process for fabricating a semiconductor device. A dielectric layer comprising at least both fluorine and nitrogen is formed overlying a substrate, in which a nitrogen content in the dielectric layer is about 5% to 10%. The dielectric layer is subsequently pattered to form at least one damascene opening therein. A metal layer is formed overlying the dielectric layer and fills the damascene opening. The excess metal layer on the dielectric layer is removed to leave the metal layer in the damascene opening. A semiconductor device with the same damascene structure is also disclosed.

    摘要翻译： 用于制造半导体器件的改进的镶嵌工艺。 形成至少包含氟和氮两者的电介质层，覆盖在基底中，其中介电层中的氮含量为约5％至10％。 随后图案化介电层以在其中形成至少一个镶嵌开口。 形成覆盖在电介质层上的金属层并填充镶嵌开口。 去除电介质层上的多余的金属层，使金属层离开镶嵌开口。 还公开了具有相同镶嵌结构的半导体器件。