公开(公告)号：US20010028243A1

公开(公告)日：2001-10-11

申请号：US09757492

申请日：2001-01-11

Applicant: FUJITSU LIMITED

Inventor： Kimitoshi Niratsuka

IPC: G01R023/175 ,  G01R023/12

CPC classification number: G01R31/3016 ,  G01R25/00

Abstract: On a semiconductor device 20, fabricated are a VCO 10A, an frequency divider by integer R 21, a frequency divider by integer (PnullNnullA) 22 wherein each of P, N and A is an integer, A is variable and A

Abstract translation: 在半导体器件20上，制作了VCO 10A，整数R 21的分频器，整数分频器（PxN + A）22，其中P，N和A分别是整数，A是可变的，A

公开(公告)号：US6154021A

公开(公告)日：2000-11-28

申请号：US218625

申请日：1998-12-22

Applicant: Johan Bergman ,  Thorsten Kraus

Inventor： Johan Bergman ,  Thorsten Kraus

IPC: G01R25/00 ,  G06G7/19

CPC classification number: G01R25/00

Abstract: The difference in phase between a first and a second electrical signal at substantially the same frequency is detected in an interval of 360.degree.. Both the first and the second signals are used as input signals to a first and a second device unambiguous detection of phase differences in an interval of 180.degree., and one input signal to the first detection device is phase-shifted ninety degrees. The output signal from the first phase detection device is used in order to indicate whether the output signal from the second phase detection device corresponds to a phase difference that is greater or smaller than 180.degree.. Also, the output signal from the second phase device is used in order to produce, with the aid of the output signal from the first phase detection device, an output signal that indicates unambiguously, in an interval of 360.degree., the value of the phase difference between the first and the second input signal.

Abstract translation: 以360°的间隔检测基本上相同频率的第一和第二电信号之间的相位差。 第一和第二信号都用作第一和第二装置的输入信号，在180度的间隔中明确地检测相位差，并且到第一检测装置的一个输入信号被相移90度。 使用来自第一相位检测装置的输出信号，以便指示来自第二相位检测装置的输出信号是否对应于大于或小于180°的相位差。 此外，使用来自第二相位装置的输出信号，以借助于来自第一相位检测装置的输出信号产生输出信号，以360度的间隔明确地指示相位值 第一和第二输入信号之间的差异。

公开(公告)号：US6114879A

公开(公告)日：2000-09-05

申请号：US226442

申请日：1999-01-06

Applicant: Andrew Popplewell ,  Stephen Williams

Inventor： Andrew Popplewell ,  Stephen Williams

IPC: H03K5/26 ,  G01R25/00 ,  G11B20/10 ,  H03L7/091 ,  H04L7/033 ,  H04L25/497 ,  H03D13/00

CPC classification number: G01R25/00 ,  H03L7/091 ,  H04L25/497 ,  H04L7/0334 ,  G11B20/10009

Abstract: A phase detector determines an error value dependent on the relative phase between a local oscillator signal, used as the system clock, and an input signal received over a PR (a, b, a) channel. The phase error value is used to control a phase locked loop (FIG. 1, not shown). The received signal is sampled at regular intervals dependent on the local oscillator signal. A threshold slicer 22 selects an ideal sample value for a sampling point by comparing the sampled value to three thresholds provided on respective ones of slicer threshold inputs 23, 24 and 25. A subtracter 27 determines a difference value corresponding to a difference between the ideal sample value and the actual sample value for that sampling point. A delay register 28 and a subtracter 29 operate to determine the sense of change to the current ideal sample value from an ideal sample value for a preceding sample point. An output of the subtractor is applied to the switching input of a switch, which thereby provides as an output signal either the difference value or the inverse of the difference value, provided by an inverter 32, dependent on the detected sense of change.

Abstract translation: 相位检测器根据用作系统时钟的本地振荡器信号和通过PR（a，b，a）通道接收的输入信号之间的相对相位来确定误差值。 相位误差值用于控制锁相环（图1，未示出）。 接收到的信号按照本地振荡器信号的规则间隔进行采样。 阈值限幅器22通过将采样值与提供在切片器阈值输入23,24和25的相应阈值上的三个阈值进行比较来选择采样点的理想采样值。减法器27确定对应于理想样本 值和该采样点的实际采样值。 延迟寄存器28和减法器29用于根据前一采样点的理想采样值确定对当前理想采样值的变化感。 减法器的输出被施加到开关的开关输入端，由此根据检测到的变化感觉，提供由逆变器32提供的差值或差值的逆的输出信号。

公开(公告)号：US6028898A

公开(公告)日：2000-02-22

申请号：US840000

申请日：1997-04-24

Applicant: Adrian Paul Sparks ,  Piers James Geoffrey Dawe ,  Robert William Spagnoletti

Inventor： Adrian Paul Sparks ,  Piers James Geoffrey Dawe ,  Robert William Spagnoletti

IPC: G01R25/00 ,  H03L7/085 ,  H04L7/033 ,  H04L27/06

CPC classification number: H03L7/085 ,  G01R25/00 ,  H04L7/033

Abstract: The invention seeks to provide an improved, bandwidth-efficient method and apparatus for acquiring and tracking bursts of data, or continuous data, of varying and unpredictable amplitude, extinction ratio, and phase.The system avoids the use of digital signal processing which is not practical at high data signal rates. The system also obviates encoding of the data signal using a line code, thereby extending the existing technology to give a significant increase in data throughput for the same available bandwidth.The system may treat acquisition of each data burst, comprising alternate synchronisation parts and data parts, ab initio.

Abstract translation: 本发明寻求提供一种改进的，带宽有效的方法和装置，用于采集和跟踪变化和不可预测的振幅，消光比和相位的数据或连续数据的突发。 该系统避免使用在高数据信号速率下不实用的数字信号处理。 该系统还使用线路代码避免了数据信号的编码，从而扩展了现有技术，以在相同的可用带宽上显着提高数据吞吐量。 系统可以从头开始处理每个数据突发的采集，包括备用的同步部分和数据部分。

公开(公告)号：US6020733A

公开(公告)日：2000-02-01

申请号：US865882

申请日：1997-05-30

Applicant: Donald A. Bradley

Inventor： Donald A. Bradley

IPC: G01R23/163 ,  G01R23/173 ,  G01R25/00 ,  G01R27/06 ,  G01R27/28 ,  G01R27/32 ,  G01R29/10 ,  H03L7/18 ,  G01R23/00

CPC classification number: G01R23/163 ,  G01R27/06 ,  G01R27/28 ,  G01R27/32 ,  G01R25/00 ,  G01R29/10

Abstract: A two port handheld VNA enabling both reflection and transmission measurements to be made over a range of 25 MHz to 3.3 GHz frequency range. The handheld VNA includes a tracking synthesizer which generates a LO signal without a direct connection to a reference oscillator, enabling resolution of the LO signal to be independent of a generated RF test signal. synchronous detectors are further included to provide incident, reflected, and transmitted IF signals to an A/D converter. To enable operation in the presence of external signals, a feedback dither line is provided from one of the synchronous detector outputs to sweep the frequency of the reference oscillator. The handheld VNA also is configured to optionally operate as a frequency monitor to determine the frequency range and power level of incoming signals without upconverting and downconverting to eliminate images as typically done in a spectrum analyzer. The frequency monitoring circuit operates by dividing the frequency range to be monitored into bins. The LO signal is then stepped for each bin until RF signals within the bin frequency range can generate an IF signal. The maximum IF signal power level detected during measurements for the bin is then stored as a power level for signals in each bin.

Abstract translation: 一个双端口手持式VNA，可在25 MHz至3.3 GHz频率范围内进行反射和透射测量。 手持式VNA包括跟踪合成器，其产生LO信号而不直接连接到参考振荡器，使得LO信号的分辨率能够独立于所产生的RF测试信号。 进一步包括同步检波器以向A / D转换器提供入射，反射和发射的IF信号。 为了在存在外部信号的情况下使能操作，从同步检测器输出之一提供反馈抖动线，以扫描参考振荡器的频率。 手持式VNA还被配置为可选地作为频率监视器操作以确定输入信号的频率范围和功率电平，而无需上变频和下变频，以消除通常在频谱分析仪中进行的图像。 频率监视电路通过将要监视的频率范围除以箱体来进行操作。 然后，LO信号对于每个仓进行步进，直到箱体频率范围内的RF信号可以产生IF信号。 然后，对于箱的测量期间检测到的最大IF信号功率电平被存储为每个仓中的信号的功率电平。

公开(公告)号：US5990673A

公开(公告)日：1999-11-23

申请号：US765595

申请日：1997-06-03

Applicant: Gunnar Forsberg

Inventor： Gunnar Forsberg

IPC: H03K5/26 ,  G01R25/00 ,  H03D13/00 ,  H03L7/085 ,  H03L7/18 ,  G01R23/12 ,  G01R25/04

CPC classification number: G01R25/00 ,  H03D13/00 ,  H03L7/085 ,  H03L7/18

Abstract: The phase difference of two periodic input signals having essentially the same frequency are measured in, for example, a communication system, in an accurate way with a high resolution and utilizing digital components. A high resolution digital phase detector which can be included in a phase locked loop comprises an oscillator providing a clock signal having a high frequency that is not an integer multiple of the frequency of the input signals. The clock signal is provided to a clock signal input of a counter, and the periodic signals are fed to the start and stop terminals of the counter. Output terminals of the counter are directly connected to inputs of a digital low-pass filter in which an average value calculation is carried out of the integer values of the output of the counter. Because of the small frequency deviation from the integer multiple value, a slow sliding of the oscillator phase compared to the phase of the input signals is achieved, such that all possible integer values on the output of the counter are run through. A very accurate calculation of the phase position is achieved by the average value calculation of these integer values in the low-pass filter. In a complete phase-locked loop, a voltage controlled oscillator provides one of the input signals to the counter through a divider circuit.

Abstract translation: PCT No.PCT / SE95 / 00813 Sec。 371日期：1997年6月3日 102（e）日期1997年6月3日PCT归档1995年6月30日PCT公布。 公开号WO96 / 01007 日期1996年1月11日具有基本上相同频率的两个周期性输入信号的相位差在例如通信系统中以高分辨率和利用数字分量的精确方式被测量。 可以包括在锁相环中的高分辨率数字相位检测器包括提供具有不是输入信号频率的整数倍的高频的时钟信号的振荡器。 时钟信号被提供给计数器的时钟信号输入，并且周期信号被馈送到计数器的起始和停止端子。 计数器的输出端子直接连接到数字低通滤波器的输入端，其中计数器的输出的整数值进行平均值计算。 由于与整数倍值的偏差小，所以实现了振荡器相位与输入信号的相位相比较慢的滑动，使得计数器的输出上的所有可能的整数值都通过。 通过低通滤波器中这些整数值的平均值计算，可以非常准确地计算相位位置。 在一个完整的锁相环中，压控振荡器通过分频电路向计数器提供一个输入信号。

公开(公告)号：US5952853A

公开(公告)日：1999-09-14

申请号：US997148

申请日：1997-12-23

Applicant: Scott D. Willingham ,  William J. McFarland

Inventor： Scott D. Willingham ,  William J. McFarland

IPC: G01R25/00 ,  H03D13/00 ,  H03K5/26 ,  H03L7/081 ,  H03L7/085 ,  H03L7/089

CPC classification number: G01R25/00 ,  H03D13/004 ,  H03L7/081 ,  H03L7/089

Abstract: A circuit for generating a signal that is proportional to the phase difference between a reference signal and a variable frequency signal. The circuit includes a reference generating circuit for generating N phase shifted reference signals from the reference signal. Each of the phase shifted reference signals has the same frequency and a different phase. The phase of the n.sup.th one of the phase shifted reference signals is equal to 360n/N degrees, where N>1 and n runs from 0 to N-1. A phase detection circuit generates a phase output signal proportional to the phase difference between the variable frequency signal and the phase shifted reference signal currently being outputted by the reference generating circuit. The phase output signal has value of I when the output signal corresponds to a phase difference of 360/N degrees. An overflow detection circuit determines when the phase output signal has an absolute value greater than I and generates a count signal and a phase adjustment signal when this situation is detected. The phase adjustment signal is coupled to the reference generating circuit and causes the reference generating circuit to select a new phase shifted reference signal. A counter is then incremented/decremented to track the accumulated phase adjustments. A digital to analog converter converts the digital value in the counter to a signal having an amplitude equal to MI, where M is the digital value. A sum circuit adds this signal to the phase output signal.

Abstract translation: 用于产生与参考信号和可变频率信号之间的相位差成比例的信号的电路。 电路包括用于从参考信号产生N个相移参考信号的参考产生电路。 每个相移参考信号具有相同的频率和不同的相位。 第n个相移参考信号的相位等于360n / N度，其中N≥1且n从0到N-1。 相位检测电路产生与参考发生电路当前正在输出的可变频率信号和相移参考信号之间的相位差成比例的相位输出信号。 当输出信号对应于360 / N度的相位差时，相位输出信号的值为I。 溢出检测电路确定相位输出信号何时具有大于I的绝对值，并且当检测到这种情况时产生计数信号和相位调整信号。 相位调整信号耦合到参考产生电路，并使基准产生电路选择新的相移基准信号。 然后计数器递增/递减，以跟踪累积的相位调整。 数模转换器将计数器中的数字值转换为幅度等于MI的信号，其中M是数字值。 总和电路将该信号添加到相位输出信号。

公开(公告)号：US5903144A

公开(公告)日：1999-05-11

申请号：US603930

申请日：1996-02-20

Applicant: Ronalf Kramer

Inventor： Ronalf Kramer

IPC: G01R25/00 ,  G01R25/08 ,  G01R31/3185 ,  H03K19/02

CPC classification number: G01R25/00 ,  G01R31/3185

Abstract: A circuit configuration for measuring a phase difference between a reference signal and a clock signal includes a first shift register being clocked by the clock signal and having an input receiving the reference signal. A digital differentiator is connected downstream of the first shift register and has an output. A counter has an input receiving the clock signal and an output outputting a multidigit binary word. A buffer memory is connected to the counter and to the digital differentiator for storing the binary word at the output of the counter in memory upon an appearance of a corresponding output signal of the digital differentiator. The buffer memory has an output forming most significant bits of an output binary word. A second shift register is inversely clocked by the clock signal and has an input receiving the reference signal and an output. An analog differentiator has an input connected to the output of the digital differentiator and an output. A D flip-flop has a data input connected to the output of the second shift register and a clock input connected to the output of the analog differentiator for supplying an output signal forming a least significant bit of the output binary word.

Abstract translation: 用于测量参考信号和时钟信号之间的相位差的电路配置包括由时钟信号计时并具有接收参考信号的输入的第一移位寄存器。 数字微分器连接在第一移位寄存器的下游并具有输出。 计数器具有接收时钟信号的输入端和输出多位二进制字的输出。 缓冲存储器连接到计数器和数字微分器，用于在出现数字微分器的相应输出信号时在存储器中的计数器的输出端存储二进制字。 缓冲存储器具有形成输出二进制字的最高有效位的输出。 第二移位寄存器由时钟信号反相时钟，并具有接收参考信号和输出的输入。 模拟微分器具有连接到数字微分器的输出和输出的输入。 A触发器具有连接到第二移位寄存器的输出的数据输入端和连接到模拟微分器的输出的时钟输入端，用于提供形成输出二进制字的最低有效位的输出信号。

公开(公告)号：US5808462A

公开(公告)日：1998-09-15

申请号：US752316

申请日：1996-11-19

Applicant: Toshiyuki Fujii ,  Shinzo Tamai ,  Hatsuhiko Naitoh ,  Naohiro Toki

Inventor： Toshiyuki Fujii ,  Shinzo Tamai ,  Hatsuhiko Naitoh ,  Naohiro Toki

IPC: G01R19/00 ,  G01R19/04 ,  G01R25/00 ,  G01R31/42 ,  H02H3/08 ,  H02H3/26

CPC classification number: G01R25/00 ,  G01R19/0053 ,  G01R31/42

Abstract: An apparatus for detecting the amplitude and phase of an a.c. signal. The apparatus includes a signal detection circuit for detecting the a.c. signal, a signal splitting circuit for splitting the detected a.c. signal into first and second a.c. signals out of phase with each other by 90.degree.. The signal splitting circuit includes a first order lag circuit having a phase lag, a subtractor, and first and second amplifying circuits. The apparatus also includes a phase compensation circuit coupled to the signal splitting circuit for receiving the first and second a.c. signals from the signal splitting circuit and for advancing the phase of an output signal of the apparatus by the phase lag of the first order lag circuit. The phase compensation circuit also includes an amplitude and phase detection circuit for detecting the amplitude and phase of the detected a.c. signal by implementing a polar coordinate transformation of the first and second a.c. signals received from the signal splitting circuit.

Abstract translation: 一种用于检测直流电压的振幅和相位的装置。 信号。 该装置包括用于检测直流电压的信号检测电路。 信号，用于分离检测到的交流电平的信号分离电路。 信号进入第一和第二个a.c. 信号异相90度。 信号分离电路包括具有相位滞后的第一级滞后电路，减法器以及第一和第二放大电路。 该装置还包括耦合到信号分离电路的相位补偿电路，用于接收第一和第二直流 来自信号分离电路的信号，并且用于使装置的输出信号的相位提前一阶滞后电路的相位滞后。 相位补偿电路还包括一个幅度和相位检测电路，用于检测检测到的交流电的幅度和相位。 通过实施第一和第二等角的极坐标变换来发出信号。 从信号分离电路接收的信号。

公开(公告)号：US5764044A

公开(公告)日：1998-06-09

申请号：US907250

申请日：1997-08-06

Applicant: Fernando Calero

Inventor： Fernando Calero

IPC: G06F7/02 ,  G01R19/00 ,  G01R19/25 ,  G01R21/133 ,  G01R25/00 ,  G01R31/00 ,  G01R31/02 ,  G06F1/02 ,  H02H3/00 ,  H02H3/38 ,  H02H3/40 ,  G01R23/175

CPC classification number: G01R19/0038 ,  G01R19/25 ,  G01R25/00 ,  H02H3/382 ,  H02H3/385 ,  G01R19/2513 ,  G01R21/133 ,  G01R31/02 ,  H02H3/003 ,  H02H3/38 ,  H02H3/402

Abstract: A numerical comparator employs numerical techniques based upon the behavior of the cylinder unit to compare phasors in real time. In one application, the torque signal generated by the numerical comparator, M.sub.k+1, is employed to determine whether a fault has occurred in a transmission line. Another application involves employing the output M.sub.k+1 to determine the direction of power flow in the transmission line. In yet another application, the output M.sub.k+1 is used to determine whether a voltage or current has exceeded a predetermined threshold. In yet another application, time dependent waveforms of positive and negative symmetrical sequence components are digitally produced.

Abstract translation: 数值比较器使用基于气缸单元的行为的数值技术来实时比较相量。 在一个应用中，由数字比较器Mk + 1产生的转矩信号用于确定传输线路中是否发生故障。 另一个应用包括采用输出Mk + 1来确定传输线中的功率流的方向。 在另一个应用中，输出Mk + 1用于确定电压或电流是否已经超过预定阈值。 在另一个应用中，数字地产生正负对称序列分量的时间相关波形。