公开(公告)号：US12022645B2

公开(公告)日：2024-06-25

申请号：US17398136

申请日：2021-08-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sukhwa Jang ,  Kanguk Kim ,  Hyunsuk Noh ,  Yeongshin Park ,  Sangkyu Sun ,  Sunyoung Lee ,  Sohyang Lee ,  Hongjun Lee ,  Hosun Jung ,  Jeongmin Jin ,  Jeonghee Choi ,  Jinseo Choi ,  Cera Hong

IPC分类号： H10B12/00

CPC分类号： H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/50

摘要： A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.

公开(公告)号：US20240196600A1

公开(公告)日：2024-06-13

申请号：US18517917

申请日：2023-11-22

申请人： Samsung Electronics Co., Ltd.

发明人： Jeongmin Jin ,  Sohyang Lee ,  Sohee Choi ,  Jinseo Choi

IPC分类号： H10B12/00

CPC分类号： H10B12/482 ,  H10B12/315 ,  H10B12/50

摘要： A semiconductor memory device includes a substrate including a plurality of active regions in a memory cell region, a plurality of bit line structures extending in parallel with each other in a first horizontal direction in the memory cell region, a plurality of buried contacts respectively and electrically connected to the active regions and partially filling a space between the bit line structures, a plurality of lower landing pads in the space between the bit line structures and respectively on the buried contacts, a landing pad insulating structure in contact with the bit line structures and the lower landing pads and including a plurality of landing pad holes, a plurality of upper landing pads respectively filling the landing pad holes and respectively connected to the lower landing pads, and a plurality of capacitor structures.

公开(公告)号：US12010827B2

公开(公告)日：2024-06-11

申请号：US17304304

申请日：2021-06-17

申请人： Micron Technology, Inc.

发明人： William M. Brewer ,  Christopher Locke ,  Kyle B. Campbell

IPC分类号： H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC分类号： H10B12/30 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B12/50

摘要： An apparatus includes fin structures comprising individual levels of a conductive material having elongated portions extending in a first horizontal direction, first conductive lines extending in a second horizontal direction transverse to the first horizontal direction, and second conductive lines extending in a vertical direction transverse to each of the first horizontal direction and the second horizontal direction. At least portions of the first conductive lines are aligned vertically. The apparatus also includes horizontal capacitor structures comprising the conductive material of the fin structures and access devices proximate intersections of the first conductive lines and the second conductive lines. The access devices comprise the conductive material of the fin structures. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

公开(公告)号：US12004341B2

公开(公告)日：2024-06-04

申请号：US17886917

申请日：2022-08-12

申请人： Micron Technology, Inc.

发明人： Sangmin Hwang ,  Si-Woo Lee

IPC分类号： H10B12/00

CPC分类号： H10B12/36 ,  H10B12/056 ,  H10B12/50

摘要： A variety of applications can include apparatus having a recessed channel FinFET. The recessed channel FinFET can include one or more fin structures between the source region and the drain region, where the one or more fin structures are recessed from a top level of the source region and from a top level of the drain region. The recessed channel FinFET can include a gate recessed from the top level of a source region and a drain region, where the gate can be separated from tip regions of the fin structures by a gate dielectric defining a channel between the source region and the drain region. Recessed channel FinFETs can be structured in a periphery to an array of a memory device and can be fabricated in a process merged with forming access lines to the array.

公开(公告)号：US20240179890A1

公开(公告)日：2024-05-30

申请号：US18374870

申请日：2023-09-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Byunghoon CHO ,  Namjung KANG ,  Kiheum NAM ,  Jihyun CHOI

IPC分类号： H10B12/00

CPC分类号： H10B12/315 ,  H10B12/482 ,  H10B12/50

摘要： A semiconductor device includes a peripheral circuit transistor disposed in a peripheral circuit region. First connection lines and second connection lines are disposed on a same plane above the peripheral circuit transistor. The second connection lines including a cutting portion. A cell capacitor is disposed on the substrate in a cell region. A first plate pattern is on the cell capacitor. A second plate pattern is on a portion of a surface of the first plate pattern. A first contact plug directly contacts an upper surface of the second plate pattern. A third connection line is disposed above the second connection line. The third connection line faces the cutting portion. Second contact plugs extend vertically to directly contact both sidewalls of the third connection line and upper surfaces of the second connection lines. The third connection line is disposed on a same plane as the second plate pattern.

公开(公告)号：US20240164081A1

公开(公告)日：2024-05-16

申请号：US18405736

申请日：2024-01-05

申请人： Samsung Electronics Co., Ltd.

发明人： Shaofeng DING ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H10B10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B12/00

CPC分类号： H10B10/18 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696 ,  H10B12/50

摘要： A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.

公开(公告)号：US20240155831A1

公开(公告)日：2024-05-09

申请号：US18339299

申请日：2023-06-22

申请人： Samsung Electronics Co., Ltd.

发明人： Jinseo Choi ,  Sohyang Lee ,  Jeongmin Jin ,  Sohee Choi

IPC分类号： H10B12/00

CPC分类号： H10B12/482 ,  H10B12/0335 ,  H10B12/50

摘要： A method of manufacturing an integrated circuit device includes forming, on a substrate, a plurality of bit line structures, which each include a bit line and an insulating capping pattern, and a plurality of contact plugs between the plurality of bit line structures, forming a plurality of recess contact plugs from the plurality of contact plugs and forming a plurality of recess spaces on the plurality of recess contact plugs, forming an engraved insulating pattern having openings, on the plurality of bit line structures and the plurality of recess contact plugs, forming a plurality of cut-off spaces by partially removing the insulating capping pattern of each bit line structure through the openings, and forming a plurality of conductive landing pads to respectively fill the plurality of recess spaces and the plurality of cut-off spaces and respectively contact upper surfaces of the plurality of recess contact plugs.

公开(公告)号：US20240154013A1

公开(公告)日：2024-05-09

申请号：US18406460

申请日：2024-01-08

申请人： Sang-Yun Lee

发明人： Sang-Yun Lee

IPC分类号： H01L29/423 ,  H01L25/18 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H10B12/00 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC分类号： H01L29/4234 ,  H01L25/18 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926 ,  H10B12/05 ,  H10B12/31 ,  H10B12/50 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

摘要： Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

公开(公告)号：US20240147709A1

公开(公告)日：2024-05-02

申请号：US18403817

申请日：2024-01-04

申请人： Samsung Electronics Co., Ltd.

发明人： Dong Oh Kim ,  Gyu Hyun Kil ,  Jung Hoon Han ,  Doo San Back

IPC分类号： H10B12/00

CPC分类号： H10B12/50 ,  H10B12/315 ,  H10B12/34

摘要： A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern disposed a top surface of the core region and a bottom surface of the first high dielectric layer.

公开(公告)号：US20240147708A1

公开(公告)日：2024-05-02

申请号：US18288413

申请日：2022-04-26

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Tatsuya ONUKI ,  Hitoshi KUNITAKE

IPC分类号： H10B12/00 ,  H01L25/065 ,  H10B10/00 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40 ,  H10B80/00

CPC分类号： H10B12/50 ,  H01L25/0657 ,  H10B10/125 ,  H10B10/18 ,  H10B12/33 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40 ,  H10B80/00

摘要： A semiconductor device having a novel structure is provided. The semiconductor device includes a first substrate provided with a first peripheral circuit having a function of driving a first memory cell and a first memory cell layer including a second substrate and a first element layer including the first memory cell. The first memory cell includes a first transistor and a first capacitor. The first transistor includes a semiconductor layer including a metal oxide in its channel formation region. The first memory cell layer is provided to be stacked over the first substrate in a direction perpendicular or substantially perpendicular to a surface of the first substrate. The second substrate includes a circuit for performing writing of data to or reading of data from the first memory cell. The first peripheral circuit and the first memory cell are electrically connected to each other through a first through electrode provided in the second substrate and the first element layer.