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公开(公告)号：US11799458B2
公开(公告)日：2023-10-24
申请号：US17693026
申请日：2022-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young O Lee , Min Su Kim , Jeong Jin Lee , Won Hyun Choi
CPC classification number: H03K3/0375 , H03K3/012 , H03K3/017
Abstract: A pulse-based flip flop circuit includes a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving either a data signal or the scan input signal responsive to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes a direct path providing a clock signal as a direct path input to a NAND circuit; a delay path including a number of plural stages that delay the clock signal and provide a delayed clock signal as a delay path input to the NAND circuit that performs a NAND operation on the direct path and delay path inputs to generate the inverted pulse signal; and a feedback path providing the pulse signal to a first stage among the stages of the delay path.
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公开(公告)号：US11796592B2
公开(公告)日：2023-10-24
申请号：US17573683
申请日：2022-01-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Denis Roland Beaudoin , Samuel Paul Visalli
IPC: G01R31/317 , H03K3/037 , G01R31/3177 , H03K19/21 , G01R31/34
CPC classification number: G01R31/31726 , G01R31/3177 , G01R31/31703 , H03K3/037 , H03K19/21
Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.
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公开(公告)号：US20230336177A1
公开(公告)日：2023-10-19
申请号：US18333284
申请日：2023-06-12
Inventor： Yu-Lun OU , Ji-Yung LIN , Yung-Chen CHIEN , Ruei-Wun SUN , Wei-Hsiang MA , Jerry Chang Jui KAO , Shang-Chih HSIEH , Lee-Chung LU
IPC: H03K19/0185 , H03K3/037
CPC classification number: H03K19/018521 , H03K3/037
Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.
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公开(公告)号：US20230336163A1
公开(公告)日：2023-10-19
申请号：US18338893
申请日：2023-06-21
Applicant: Huawei Technologies Co., Ltd.
Inventor： Sheng Chen , Theng Tee Yeo
Abstract: A multi-phase clock generation circuit is configured to generate a multi-phase non-overlapping clock signal and includes a loop structure, where input ends and output ends of a plurality of logic gates are electrically coupled head to tail to form the loop structure; and a plurality of latches configured to latch signals at the input ends of the logic gates. The multi-phase clock generation circuit performs a logical operation based on selection signals and clock signals that are received at the logic gates, latches data of upper-stage logic gates that is received at logic gates in a loop through the latches, and outputs multi-phase non-overlapping clock signals through the output ends of the logic gates.
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公开(公告)号：US11791819B2
公开(公告)日：2023-10-17
申请号：US16727742
申请日：2019-12-26
Applicant: Intel Corporation
Inventor： Steven Hsu , Amit Agarwal , Simeon Realov , Ram Krishnamurthy
CPC classification number: H03K19/0016 , G11C7/222 , H03K3/012 , H03K3/0372 , H03K5/135 , H03K19/0013
Abstract: A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization. The static pass-gate master-slave flip-flop utilizes novel layout optimization enabling significant power reduction. The layout removes the clock poly over notches in the diffusion area. Poly lines implement clock nodes. The poly lines are aligned between n-type and p-type active regions.
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Patent Agency Ranking
96.发明公开公开(公告)号：US20230327675A1
公开(公告)日：2023-10-12
申请号：US18042208
申请日：2021-07-23
Inventor： Yinghan YANG , Zixun ZHANG
Abstract: A computing apparatus triggered by an edge of a supply-line signal with a pulse width counter includes: a clock circuit to supply clock signals to a pulse width counter from an output port of said clock circuit; said pulse width counter triggered by said clock signals to count the pulse width of a supply-line signal from a power supply line, to set a circuit status of said computing apparatus in accordance with said pulse width, and to output said circuit status to an edge-triggered computing unit; and the edge-triggered computing unit to do computing triggered by an edge of a supply-line signal, and to output computing result as the output of said computing apparatus in accordance with said circuit status. The circuit status of the computing apparatus is set in accordance with pulse width counter of supply-line signals .
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公开(公告)号：US20230327657A1
公开(公告)日：2023-10-12
申请号：US18025155
申请日：2021-09-08
Applicant: Nordic Semiconductor ASA
Inventor： Ruben Undheim
CPC classification number: H03K5/26 , H03K2005/00058 , H03L7/08 , H03K3/037
Abstract: An electronic device comprises a synchronisation system that receives a signal clocked by a first clock signal having a first frequency and receives a second clock signal having said first frequency, but offset in phase from the first clock signal. The signal is delayed by an adjustable delay period. It is determined whether, following a logic transition in the delayed signal, the next clock edge received is an active edge or is a non-active edge. A calibration controller increases the delay period when the next clock edge is a non-active edge and maintains or decreases the delay period when the next clock edge is an active edge, or decreases the delay period when the next clock edge is an active edge and maintains or increases the delay period when the next clock edge is a non-active edge.
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公开(公告)号：US11777477B2
公开(公告)日：2023-10-03
申请号：US17238245
申请日：2021-04-23
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Chi-Fu Chang
CPC classification number: H03K5/00006 , G01R19/10 , G06F1/08 , G06F1/30 , H02H1/0007 , H03K3/037 , H03K2005/00078
Abstract: A digital circuit device includes a power supply circuitry, a digital circuitry, a digital circuitry, and a protection circuitry. The power supply circuitry is configured to output a supply voltage. The digital circuitry is configured to be driven by the supply voltage, and is configured to perform at least one operation according to a first clock signal. The protection circuitry is configured to generate the first clock signal according to at least one of a voltage drop of the supply voltage and a load signal sent from the digital circuitry.
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公开(公告)号：US11770116B1
公开(公告)日：2023-09-26
申请号：US17888586
申请日：2022-08-16
Applicant: Texas Instruments Incorporated
Inventor： Madusudanan Srinivasan Gopalan , Robert Karl Butler
Abstract: A duty cycle correction circuit, and method of operating the same, to correct the duty cycle of an input clock signal having a frequency divided-down from a reference clock by an odd-valued integer. A delay stage outputs the input clock signal delayed by one half-cycle of the reference clock, and a logic circuit outputs an extended clock signal by a logical OR of the input and delayed clock signals. A latch latches the extended clock signal when enabled by the reference clock, and a flip-flop latches the extended clock signal responsive to the reference clock. A gate selects the latch output or the flip-flop output based on the state of the delayed clock signal as an intermediate signal. A multiplexer generates the output clock by selecting between the intermediate signal and the input clock signal in alternating reference clock phases.
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公开(公告)号：US20230299754A1
公开(公告)日：2023-09-21
申请号：US17696352
申请日：2022-03-16
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
IPC: H03K3/037
CPC classification number: H03K3/037
Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.
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