公开(公告)号：US10593878B2

公开(公告)日：2020-03-17

申请号：US16107338

申请日：2018-08-21

申请人： SK hynix Inc.

发明人： Kyoung Su Choi

IPC分类号： H01L21/00 ,  H01L21/16 ,  H01L45/00 ,  G11C7/18 ,  G11C8/14 ,  H01L27/24 ,  H01L27/22

摘要： An electronic device includes a semiconductor memory, wherein the semiconductor memory comprises a plurality of memory stacks neighboring each other in a first direction and a second direction, the second direction intersecting the first direction, a plurality of first liner layers covering sidewalls of memory stacks that neighbor each other in the second direction, the plurality of first liner layers extending in the second direction, a plurality of first air gaps located in spaces covered by the first liner layers, and a plurality of second air gaps located between each pair of memory stacks that neighbor each other in the first direction, the plurality of second air gaps extending in the second direction.

公开(公告)号：US20200066986A1

公开(公告)日：2020-02-27

申请号：US16529573

申请日：2019-08-01

申请人： Micron Technology, Inc.

发明人： Paolo Fantini ,  Marco Bernasconi ,  Silvia Gabardi

IPC分类号： H01L45/00 ,  G11C13/00 ,  G11C8/14 ,  G11C7/18

摘要： Methods, systems, and devices for operating memory cell(s) using transition metal doped GST are described. As discussed herein, a composition including germanium (Ge), antimony (Sb), tellurium (Te), and at least one of yttrium (Y) and scandium (Sc) may be used as a memory element in a memory cell. For example, a memory element may include a composition having Ge in an amount ranging from 15 to 35 atomic percent (at. %) of the composition, Sb in an amount less than or equal to 50 at. % of the composition, Te in an amount greater than or equal to 40 at. % of the composition, and at least one of Y and Sc in an amount ranging from 0.15 to 10 at. % of the composition.

公开(公告)号：US20200066340A1

公开(公告)日：2020-02-27

申请号：US16107063

申请日：2018-08-21

申请人： Hewlett Packard Enterprise Development LP

发明人： Amit S. Sharma ,  Suhas Kumar ,  Xia Sheng

IPC分类号： G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  G11C8/14

摘要： A memristor device includes a first electrode, a second electrode, and a memristor layer disposed between the first electrode and the second electrode. The memristor layer is formed of a metal oxide. The memristor layer includes a plurality of regions that extend between the first electrode and the second electrode. The plurality of regions of the memristor layer are created with different concentrations of oxygen before electrical operation, and, during electrical operation, a voltage-conductance characteristic of the memristor device is controlled based on the different concentrations of oxygen of the plurality of regions. The controlling of the voltage-conductance characteristic includes increasing or decreasing the conductance of the memristor device toward a target conductance at a specific voltage.

公开(公告)号：US10559573B2

公开(公告)日：2020-02-11

申请号：US16162340

申请日：2018-10-16

申请人： UNITED MICROELECTRONICS CORP.

发明人： Shu-Ru Wang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chien-Hung Chen ,  Chun-Hsien Huang ,  Li-Ping Huang ,  Chun-Yen Tseng ,  Meng-Ping Chuang

IPC分类号： H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  G11C8/14 ,  G11C7/18 ,  H01L27/02 ,  H01L27/12 ,  H01L27/092

摘要： A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

公开(公告)号：US10546641B1

公开(公告)日：2020-01-28

申请号：US16214007

申请日：2018-12-07

申请人： Micron Technology, Inc.

发明人： Allahyar Vahidimowlavi ,  Kalyan C. Kavalipurapu

IPC分类号： G11C16/08 ,  G11C8/14 ,  G11C5/06 ,  G11C16/12 ,  G11C16/04 ,  G11C8/08

摘要： Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.

公开(公告)号：US20200020377A1

公开(公告)日：2020-01-16

申请号：US16583029

申请日：2019-09-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Chieh MO ,  Shih-Chi KUO

IPC分类号： G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  G11C7/18 ,  G11C8/14

摘要： Vertical memory cells and memory devices using the same are disclosed. In one example, a memory cell formed on a backend layer over a substrate is disclosed. The memory cell includes: a first electrode, a second electrode and a magnetic tunnel junction. The first electrode has sidewalls and a bottom surface disposed over the backend layer. The second electrode has sidewalls and a bottom surface in contact with the backend layer. The magnetic tunnel junction is formed between the first electrode and the second electrode. The magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

公开(公告)号：US20200013465A1

公开(公告)日：2020-01-09

申请号：US16512067

申请日：2019-07-15

申请人： Micron Technology, Inc.

发明人： Koji Sakui

IPC分类号： G11C16/04 ,  G11C5/06 ,  G11C8/08 ,  G11C8/14 ,  G11C16/08 ,  G11C16/14 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

摘要： Some embodiments include apparatuses and methods using a substrate, a first memory cell block including first memory cell strings located over the substrate, first data lines coupled to the first memory cell strings, a second memory cell block including second memory cell strings located over the first memory cell block, second data lines coupled to the second memory cell strings, first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus, and second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry. No conductive path of the first and second conductive paths is shared by the first and second memory cell blocks.

公开(公告)号：US10510417B2

公开(公告)日：2019-12-17

申请号：US16101904

申请日：2018-08-13

申请人： Toshiba Memory Corporation

发明人： Kazuharu Yamabe ,  Tatsuo Izumi

IPC分类号： G11C16/26 ,  G11C16/14 ,  G11C8/14 ,  G11C7/18 ,  H01L27/1157 ,  G11C16/08 ,  G11C16/04

摘要： According to one embodiment, a semiconductor memory device includes: a first memory unit including first and second memory cells; a second memory unit including third and fourth memory cells; a third memory unit including fifth and sixth memory cells; a first word line coupled to gates of the first, third, and fifth memory cells; and a second word line coupled to gates of the second, fourth, and sixth memory cells. In a write operation, the first memory cell, the third memory cell, the fifth memory cell, the sixth memory cell, the fourth memory cell, and the second memory cell are written in this order.

公开(公告)号：US20190287997A1

公开(公告)日：2019-09-19

申请号：US16127634

申请日：2018-09-11

申请人： Toshiba Memory Corporation

发明人： Reiko Komiya ,  Tatsuo Izumi ,  Takaya Yamanaka ,  Takeshi Nagatomo ,  Karin Takagi

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  G11C7/18 ,  G11C8/14

摘要： A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.

公开(公告)号：US10418105B2

公开(公告)日：2019-09-17

申请号：US15620886

申请日：2017-06-13

申请人： SK hynix Inc.

发明人： Sun Kyu Park ,  Min Kyu Lee

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C8/12 ,  G11C8/14 ,  H01L27/11524

摘要： Disclosed is a semiconductor memory device. The semiconductor memory device includes: a first memory block; and a second memory block sharing a block word line with the first memory block, in which the block word line includes a first block word line disposed so as to overlap the first memory block and a second block word line disposed so as to overlap the second memory block. According to the present disclosure, it is less likely to have an operation failure.