公开(公告)号：US20170203960A1

公开(公告)日：2017-07-20

申请号：US15327902

申请日：2015-08-20

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Errong JING

IPC: B81B7/02 ,  G01J1/42 ,  G01J1/04 ,  B81C1/00

CPC classification number: B81B7/02 ,  B81B2201/0278 ,  B81B2203/0118 ,  B81C1/00 ,  B81C1/0015 ,  B81C2201/0197 ,  G01J1/04 ,  G01J1/42 ,  G01J5/024 ,  G01J5/0853

Abstract: A method for manufacturing a MEMS double-layer suspension microstructure comprises steps of: forming a first film body on a substrate, and a cantilever beam connected to the substrate and the first film body; forming a sacrificial layer on the first film body and the cantilever beam; patterning the sacrificial layer located on the first film body to manufacture a recessed portion used for forming a support structure, the bottom of the recessed portion being exposed of the first film body; depositing a dielectric layer on the sacrificial layer; patterning the dielectric layer to manufacture a second film body and the support structure, the support structure being connected to the first film body and the second film body; and removing the sacrificial layer to obtain the MEMS double-layer suspension microstructure.

公开(公告)号：US20170131116A1

公开(公告)日：2017-05-11

申请号：US15321958

申请日：2015-06-26

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Huagang WU

IPC: G01C25/00 ,  G01C19/56

CPC classification number: G01C25/00 ,  G01C19/56 ,  G01C19/5776

Abstract: A method for correcting the driving amplitude of a gyro sensor, mainly comprises adjusting the size of a driving signal (a preset amplitude value) through feedback of a sensor response amplitude signal (an average amplitude value) in a resonance maintaining time period, so that the response amplitude of the resonance maintaining time period tends to be equal, and a stable resonance amplitude is maintained. Also provided is a system for correcting the driving amplitude of a gyro sensor.

公开(公告)号：US09595520B2

公开(公告)日：2017-03-14

申请号：US14901622

申请日：2014-06-09

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xiaoshe Deng ,  Shuo Zhang ,  Qiang Rui ,  Genyi Wang

IPC: H01L29/74 ,  H01L27/07 ,  H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8249 ,  H01L29/868 ,  H01L29/40

CPC classification number: H01L27/0727 ,  H01L21/8249 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/868

Abstract: An insulated gate bipolar translator (IGBT) with a built-in diode and a manufacturing method thereof are provided. The IGBT comprises: a semiconductor substrate (1) of the first conduction type which has a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises an active region (100) and a terminal protection area (200) which is located at the outer side of the active region; an insulated gate transistor unit which is formed at the side of the first major surface (1S1) of the active region (100), wherein a channel of the first conduction type is formed thereon during the conduction thereof; and first semiconductor layers (10) of the first conduction type and second semiconductor layers (11) of the second conduction type of the active region, which are formed at the side of the second major surface (1S2) of the semiconductor substrate (1) alternately, wherein the IGBT only comprises the second semiconductor layers (11) in the terminal protection area (200) which is located at the side of the second major surface (1S2) of the semiconductor substrate (1).

Abstract translation: 提供了具有内置二极管的绝缘栅双极转换器（IGBT）及其制造方法。 IGBT包括：具有第一主表面（1S1）和第二主表面（1S2）的第一导电类型的半导体衬底（1），其中半导体衬底（1）包括有源区（100）和端子 保护区域（200），其位于有源区域的外侧; 绝缘栅晶体管单元，其形成在有源区（100）的第一主表面（1S1）侧，其中在其导通期间在其上形成第一导电类型的沟道; 以及形成在半导体衬底（1）的第二主表面（1S2）侧的第一导电类型和第二导电类型的有源区的第二半导体层（11）的第一半导体层（10） 交替地，其中IGBT仅包括端子保护区域（200）中位于半导体衬底（1）的第二主表面（1S2）侧的第二半导体层（11）。

公开(公告)号：US09590029B2

公开(公告)日：2017-03-07

申请号：US14902432

申请日：2014-08-25

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong Zhong ,  Dongfei Zhou ,  Xiaoshe Deng ,  Genyi Wang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/40 ,  H01L29/16 ,  H01L29/20 ,  H01L29/161 ,  H01L29/04 ,  H01L21/761

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/401 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396

Abstract: A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a polysilicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.

Abstract translation: 一种用于制造绝缘栅双极晶体管（100）的方法，包括：提供衬底（10），在衬底（10）的前表面上形成场氧化物层（20），并形成端子保护环（23）; 通过使用有源区光掩模对有源区域氧化物层（20）进行光刻和蚀刻，通过使用光致抗蚀剂作为掩模膜将N型离子引入到衬底（10）中; 在所述场氧化物层（20）的蚀刻衬底（10）上沉积和形成多晶硅栅极（31），并在所述多晶硅栅极（31）上形成保护层; 在N型离子的导入区域上进行接合，然后形成载流子增强区域（41）。 通过使用P阱光掩模进行光蚀刻，将P型离子引入载体增强区域（41）中，并执行连接推动然后形成P体区域; 通过多晶硅栅极进行N型离子的自对准引入到P体区域中，并进行结压并形成N型重掺杂区域; 在所述多晶硅栅极的两侧形成侧壁，将P型离子引入所述N型重掺杂区域中，并执行结推进，然后形成P型重掺杂区域; 并去除保护层，然后进行多晶硅栅极的引入和掺杂。 该方法减少了设置载流子增强区域的正向压降。

公开(公告)号：US20170062405A1

公开(公告)日：2017-03-02

申请号：US15308574

申请日：2015-05-04

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng ZHANG ,  Sen ZHANG

IPC: H01L27/02 ,  H01L23/535 ,  H01L29/739

CPC classification number: H01L27/027 ,  H01L23/535 ,  H01L23/60 ,  H01L27/0266 ,  H01L29/7393 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device 101, the ESD protection structure is a NMOS transistor 102, a drain of the NMOS transistor is shared by a source of the power device as a common-drain-source structure 107, substrate leading-out regions of the power device 101 and the NMOS transistor are coupled to the source 106 of the NMOS transistor as a ground leading-out. In the present disclosure, the drain of the NMOS transistor is shared by the source of the power device, so the increased area of the device with the ESD protection structure incorporated is small. In addition, the holding voltage at the source of the high-voltage power device is relatively low, which helps to protect the gate oxide and improve the source reliability.

Abstract translation: 本公开涉及具有ESD保护结构的半导体器件。 半导体器件包括高电压功率器件101，ESD保护结构是NMOS晶体管102，NMOS晶体管的漏极作为共漏极 - 源极结构107由功率器件的源共享， 功率器件101和NMOS晶体管的输出区域作为接地引出耦合到NMOS晶体管的源极106。 在本公开内容中，NMOS晶体管的漏极由功率器件的源共享，因此具有包含ESD保护结构的器件的增加的面积很小。 另外，高压功率器件源极的保持电压相对较低，有助于保护栅极氧化物，提高源极可靠性。

公开(公告)号：US09553164B2

公开(公告)日：2017-01-24

申请号：US14902205

申请日：2014-06-13

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xuan Huang ,  Wanli Wang ,  Genyi Wang

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/10 ,  H01L21/304 ,  H01L21/306 ,  H01L29/08 ,  H01L29/49 ,  H01L23/31 ,  H01L29/739

CPC classification number: H01L29/66333 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30625 ,  H01L23/3171 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/4916 ,  H01L29/7395

Abstract: A method for manufacturing an IGBT, comprising: providing a substrate having a first surface and a second surface and of a first or second type of electrical conductance; forming grooves at intervals on the first surface of the substrate; filling a semiconductor material of the second or first type of electrical conductance into the grooves to form channels, where the type of electrical conductance of the channels is different from the type of electrical conductance of the substrate; bonding on the first surface of the substrate to form a drift region of the second type of electrical conductance; forming a front-side structure of the IGBT on the basis of the drift region; thinning the substrate starting from the second surface of the substrate until the channels are exposed; and forming a rear-side metal electrode on the channels and the thinned substrate. The method has no specific requirement with respect to sheet flow capacity, nor requires a double-sided exposure machine apparatus, is compatible with a conventional process, and has a simple process and high efficiency.

Abstract translation: 一种制造IGBT的方法，包括：提供具有第一表面和第二表面以及第一或第二类型电导的基板; 在基板的第一表面上间隔地形成槽; 将第二或第一类电导体的半导体材料填充到沟槽中以形成通道，其中通道的导电类型不同于衬底的电导的类型; 在所述衬底的所述第一表面上接合以形成所述第二类型电导的漂移区域; 基于漂移区域形成IGBT的前侧结构; 从衬底的第二表面开始稀释衬底，直到通道暴露; 以及在通道和薄化的基板上形成后侧金属电极。 该方法对于纸张流动能力没有特别要求，也不需要双面曝光机装置，与常规方法兼容，并且具有简单的工艺和高效率。

公开(公告)号：US20170011957A1

公开(公告)日：2017-01-12

申请号：US15119289

申请日：2015-04-29

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Zhiyong WANG ,  Dejin WANG ,  Jingjing MA

IPC: H01L21/768 ,  H01L27/12 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/76801 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer (54) covering a metal interconnect, a fluorine-silicon glass layer on the silicon-rich oxide layer, and a non-doped silicate glass layer on the fluorine-silicon glass layer; the thickness of the silicon-rich oxide layer (54) is 700 angstroms ±10%; the silicon-rich oxide layer having a greater thickness captures movable ions on an unsaturated bond, such that it is difficult for the movable ions to pass through the silicon-rich oxide layer, thus blocking the movable ions. The present invention has good performance in an integrity evaluation of the gate oxide layer, and avoids damage to the device caused by the aggregation of movable ions at an interface. Also provided are a silicon-on-insulator device and a method of manufacturing the intermetallic dielectric layer of the silicon-on-insulator device.

Abstract translation: 提供一种绝缘体上硅器件的金属间介电层结构，其包括覆盖金属互连的富硅氧化物层（54），富硅氧化物层上的氟硅玻璃层和非掺杂氧化物层 氟硅玻璃层上的硅酸盐玻璃层; 富硅氧化物层（54）的厚度为700埃±10％; 具有较大厚度的富硅氧化物层捕获不饱和键上的可移动离子，使得可移动离子难以通过富硅氧化物层，从而阻挡可移动离子。 本发明在栅极氧化物层的完整性评价中具有良好的性能，并且避免了由界面处的可移动离子聚集引起的器件损坏。 还提供了绝缘体上硅器件和制造绝缘体上硅器件的金属间介电层的方法。

公开(公告)号：US09543451B2

公开(公告)日：2017-01-10

申请号：US14407599

申请日：2013-06-10

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangtao Han

IPC: H01L29/808 ,  H01L29/10 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/808 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/402

Abstract: The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer. Wherein a drain electrode electrically is led out from the second conductivity type drain heavily doped region; a source electrode electrically is led out from a connection of the field electrode plate and the second conductivity type source heavily doped region; and a gate electrode electrically is led out from the first conductivity type gate heavily doped region. The transistor has a high breakdown voltage and easy to be integrated.

Abstract translation: 本发明公开了一种高电压JFET。 高电压JFET包括位于第一导电型外延层上的第二导电类型漂移区; 位于所述第二导电型漂移区域中的第二导电型漏极重掺杂区域; 位于所述第二导电型漂移区和所述第二导电型漏极重掺杂区的一侧的漏极端氧区; 位于第二导电型漂移区侧的第一导电型阱区; 第二导电型源极重掺杂区域和位于第一导电类型阱区域上的第一导电类型栅极重掺杂区域和栅极源极氧区域; 位于所述第二导电型源极重掺杂区域和所述第二导电型漂移区域之间的第二导电型沟道层; 位于第二导电型沟道层上的电介质层和场电极板。 其中漏极电极从第二导电类型漏极重掺杂区域引出; 源极电极从场电极板和第二导电类型源重掺杂区域的连接引出; 并且从第一导电型栅极重掺杂区域引出栅电极。 晶体管具有高击穿电压，易于集成。

公开(公告)号：US20160380072A1

公开(公告)日：2016-12-29

申请号：US14902517

申请日：2014-07-22

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong ZHONG ,  Xiaoshe DENG ,  Genyi WANG ,  Dongfei ZHOU

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/265 ,  H01L29/739 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/66333 ,  H01L21/02233 ,  H01L21/26513 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7395

Abstract: An insulated gate bipolar transistor and a manufacturing method therefor. The insulated gate bipolar transistor comprises a semiconductor substrate (1) of a first conductive type, which is provided with a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises a primitive cell area (2) and a terminal protection area (4) which is located outside the primitive cell area; a first semiconductor layer (5) of a first conductive type which is formed at the side of the first major surface of the semiconductor substrate (1), wherein the doping concentration of the first semiconductor layer (5) is higher than the doping concentration of the semiconductor substrate (1); and an insulated gate transistor unit which is formed at the side of the first major surface of the first semiconductor layer (5) in the primitive cell area, wherein the insulated gate transistor unit is conducted, a channel of a first conductive type is formed. Compared with the prior art, the present invention not only can improve the voltage resistance reliability of the insulted gate bipolar transistor, but also can reduce the forward conductive voltage drop of the insulated gate bipolar transistor.

Abstract translation: 一种绝缘栅双极晶体管及其制造方法。 绝缘栅双极晶体管包括具有第一主表面（1S1）和第二主表面（1S2）的第一导电类型的半导体衬底（1），其中半导体衬底（1）包括原始单元区域 （2）和位于原始单元区域外部的端子保护区域（4）; 形成在半导体衬底（1）的第一主表面侧的第一导电类型的第一半导体层（5），其中第一半导体层（5）的掺杂浓度高于 半导体衬底（1）; 以及绝缘栅晶体管单元，其形成在原电池区域中的第一半导体层（5）的第一主表面侧，其中绝缘栅晶体管单元导通，形成第一导电类型的沟道。 与现有技术相比，本发明不仅可以提高绝缘栅双极晶体管的耐电压可靠性，而且可以降低绝缘栅双极晶体管的正向导通电压降。

公开(公告)号：US20160379974A1

公开(公告)日：2016-12-29

申请号：US14902519

申请日：2014-08-19

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shuo ZHANG ,  Qiang RUI ,  Genyi WANG ,  Xiaoshe DENG

IPC: H01L27/06 ,  H01L29/739 ,  H01L29/06 ,  H01L21/265 ,  H01L21/304 ,  H01L29/10 ,  H01L29/66 ,  H01L21/3065

CPC classification number: H01L27/0664 ,  H01L21/263 ,  H01L21/26513 ,  H01L21/304 ,  H01L21/3065 ,  H01L29/0638 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

Abstract: A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for filling in grooves on the back of a reverse conducting insulated gate bipolar transistor. The parameters of reverse conducting diodes on the back of the reverse conducting insulated gate bipolar transistor can be controlled simply by controlling the doping concentration of the polysilicon accurately, indicating relatively low requirements for process control. The reverse conducting insulated gate bipolar transistor manufacturing method is relatively low in requirements for process control and relatively small in manufacturing difficulty.

Abstract translation: 一种用于反向导通绝缘栅双极晶体管的制造方法，其制造方法的特征在于使用多晶硅来填充反向导通绝缘栅双极晶体管背面的沟槽。 反向导通绝缘栅双极晶体管背面的反向导通二极管的参数可以简单地通过精确控制多晶硅的掺杂浓度来控制，从而对过程控制要求相对较低。 反向导通绝缘栅双极晶体管制造方法对于工艺控制的要求相对较低，制造难度相对较小。