公开(公告)号：US20100265773A1

公开(公告)日：2010-10-21

申请号：US12705158

申请日：2010-02-12

Applicant: HSIANG-LAN LUNG ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Hang-Ting Lue

Inventor： HSIANG-LAN LUNG ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Hang-Ting Lue

IPC: G11C16/04 ,  H01L21/76

CPC classification number: G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

Abstract translation: 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

公开(公告)号：US20100221851A1

公开(公告)日：2010-09-02

申请号：US12777858

申请日：2010-05-11

Applicant: Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

Inventor： Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L2224/73204 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.

Abstract translation: 半导体工艺测试结构包括电极，电荷俘获层和扩散区域。 测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。 然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

公开(公告)号：US20100165711A1

公开(公告)日：2010-07-01

申请号：US12345384

申请日：2008-12-29

Applicant: MING-HSIU LEE

Inventor： MING-HSIU LEE

IPC: G11C11/00

CPC classification number: G11C13/0038 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.

Abstract translation: 这里描述了用于操作这样的设备的存储器件和方法。 本文描述了一种用于操作包括相变材料并且可编程为包括高电阻状态和较低电阻状态的多个电阻状态的存储单元的方法。 该方法包括将第一偏置装置施加到存储器单元以建立较低电阻状态，第一偏置装置包括第一电压脉冲。 该方法还包括确定存储器单元是否处于较低电阻状态，并且如果存储单元不处于较低电阻状态，则向存储单元施加第二偏置布置。 第二偏置装置包括具有大于第一电压脉冲的脉冲高度的第二电压脉冲。

公开(公告)号：US07656701B2

公开(公告)日：2010-02-02

申请号：US11894869

申请日：2007-08-21

Applicant: Ming Hsiu Lee ,  Yi Chou Chen

Inventor： Ming Hsiu Lee ,  Yi Chou Chen

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0092

Abstract: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.

Abstract translation: 编程相变装置的方法包括选择期望的阈值电压（Vth）并将编程脉冲施加到相变装置中的相变材料。 应用编程脉冲包括向相变材料施加一定量的能量以将该材料的至少一部分驱动在熔化能级以上。 施加到相变材料的能量的一部分被允许消散在熔融能级以下。 控制来自相变材料的能量耗散的形状，直到施加到相变材料的能量小于淬火能量水平，以使相变装置具有期望的Vth。 施加到相变材料的能量的剩余部分被允许消散到环境水平。

公开(公告)号：US07652914B2

公开(公告)日：2010-01-26

申请号：US11651157

申请日：2007-01-09

Applicant: Thomas Nirschl ,  Roger Cheek ,  Mark Lamorey ,  Ming-Hsiu Lee

Inventor： Thomas Nirschl ,  Roger Cheek ,  Mark Lamorey ,  Ming-Hsiu Lee

IPC: G11C11/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C2213/74 ,  G11C2213/79

Abstract: A memory includes a bit line and a phase change element. A first side of the phase change element is coupled to the bit line. The memory includes a first access device coupled to a second side of the phase change element and a second access device coupled to the second side of the phase change element. The memory includes a circuit for precharging the bit line and one of selecting only the first access device to program the phase change element to a first state and selecting both the first access device and the second access device to program the phase change element to a second state.

Abstract translation: 存储器包括位线和相变元件。 相变元件的第一侧耦合到位线。 存储器包括耦合到相变元件的第二侧的第一存取装置和耦合到相变元件的第二侧的第二存取装置。 存储器包括用于对位线进行预充电的电路和仅选择第一存取装置以将相变元件编程为第一状态的电路，并且选择第一存取装置和第二存取装置以将相变元件编程为第二 州。

公开(公告)号：US07626858B2

公开(公告)日：2009-12-01

申请号：US11450605

申请日：2006-06-09

Applicant: Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

Inventor： Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

Abstract: A memory includes a phase change element having a first side and a second side and a first line coupled to the first side of the element. The memory includes an access device coupled to the second side of the element and a second line coupled to the access device for controlling the access device. The memory includes a circuit for precharging the first line to a first voltage and for applying a voltage pulse to the second line such that a current pulse is generated through the access device to the element to program the element to a selected one of more than two states. The voltage pulse has an amplitude based on the selected state.

Abstract translation: 存储器包括具有第一侧和第二侧以及耦合到元件的第一侧的第一线的相变元件。 存储器包括耦合到元件的第二侧的访问设备和耦合到访问设备的用于控制访问设备的第二行。 存储器包括用于将第一线路预充电到第一电压并且用于将电压脉冲施加到第二线路的电路，使得通过该接入装置向该元件生成电流脉冲以将该元件编程为多于两个中的所选择的一个 状态。 电压脉冲具有基于选择状态的幅度。

公开(公告)号：US07324377B2

公开(公告)日：2008-01-29

申请号：US10976668

申请日：2004-10-29

Applicant: Ming Hsiu Lee

Inventor： Ming Hsiu Lee

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3418

Abstract: A method is described for erasing a selected data region in an NROM cell that is a member of a virtual ground NROM EEPROM array. The method provides that erasing the selected data region does not disturb the program state of unselected data regions.

Abstract translation: 描述了用于擦除作为虚拟接地NROM EEPROM阵列的成员的NROM单元中的选定数据区的方法。 该方法提供擦除所选择的数据区域不会干扰未选择的数据区域的编程状态。

公开(公告)号：US20070291551A1

公开(公告)日：2007-12-20

申请号：US11530585

申请日：2006-09-11

Applicant: Hao-Ming Lien ,  Ming-Hsiu Lee

Inventor： Hao-Ming Lien ,  Ming-Hsiu Lee

IPC: G11C16/04

CPC classification number: G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

Abstract: A mixed nonvolatile memory array. In the mixed nonvolatile memory array, each nonvolatile memory cell has at least one depletion mode memory cell. The depletion mode region is composed of a gate structure and a doped region. Since the thickness of the doped region is relatively thin, a voltage is applied on the gate structure to invert the conductive type of the doped region under the gate structure. Meanwhile, a bias is applied at both terminals of the doped region so as to control the operation of the depletion mode memory cell. In addition, each nonvolatile memory cell of the mixed nonvolatile memory array further comprises an enhanced mode memory cell. Therefore, each nonvolatile memory cell provides at least four carrier storage spaces so that the numbers of bits storing in a unit memory device is increased.

Abstract translation: 混合非易失性存储器阵列。 在混合非易失性存储器阵列中，每个非易失性存储单元具有至少一个耗尽型存储单元。 耗尽模式区域由栅极结构和掺杂区域组成。 由于掺杂区域的厚度相对较薄，所以在栅极结构上施加电压以反转栅极结构下的掺杂区域的导电类型。 同时，在掺杂区域的两个端子处施加偏压，以便控制耗尽型存储单元的工作。 此外，混合非易失性存储器阵列的每个非易失性存储单元还包括增强型存储单元。 因此，每个非易失性存储单元提供至少四个载波存储空间，使得存储在单元存储器件中的位数增加。

公开(公告)号：US07301219B2

公开(公告)日：2007-11-27

申请号：US11146777

申请日：2005-06-06

Applicant: Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

Inventor： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

IPC: H01L29/00 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L29/7885 ,  H01L29/7887 ,  H01L29/7923 ,  Y10S257/90

Abstract: An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to the first N+ doped junction and under the composite charge trapping layer. A P− doped region is positioned adjacent to the second N+ doped junction and under the composite charge trapping layer. The asymmetrically doped memory cell will store charges at the end of the composite charge trapping layer that is above the P− doped region. The asymmetrically doped memory cell can function as an electrically erasable programmable read only memory cell, and is capable of multiple level cell operations. A method for making an asymmetrically doped memory cell is also described.

Abstract translation: 不对称掺杂的存储单元在P衬底上具有第一和第二N +掺杂结。 复合电荷捕获层设置在P衬底上并且在第一和第二N +掺杂结之间。 N掺杂区域邻近第一N +掺杂结并位于复合电荷俘获层下方。 P-掺杂区域邻近第二N +掺杂结并位于复合电荷俘获层下方。 非对称掺杂的存储单元将在复合电荷捕获层的末端在P掺杂区域之上存储电荷。 非对称掺杂的存储单元可以用作电可擦除可编程只读存储器单元，并且能够进行多级单元操作。 还描述了制造非对称掺杂的存储单元的方法。

公开(公告)号：US07272037B2

公开(公告)日：2007-09-18

申请号：US10976648

申请日：2004-10-29

Applicant: Ming Hsiu Lee ,  Yi Chou Chen

Inventor： Ming Hsiu Lee ,  Yi Chou Chen

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0092

Abstract: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.