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    Techniques and configurations to impart strain to integrated circuit devices
    101.
    发明授权
    Techniques and configurations to impart strain to integrated circuit devices 有权
    赋予集成电路器件应变的技术和配置

    公开(公告)号：US08633470B2

    公开(公告)日：2014-01-21

    申请号：US12646697

    申请日：2009-12-23

    Applicant: Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

    Inventor： Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

    IPC: H01L29/06

    CPC classification number: H01L29/7782 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848

    Abstract: Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例描述了为诸如水平场效应晶体管等集成电路器件施加应变的技术和配置。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一势垒层，耦合到第一势垒层的量子阱沟道，量子阱沟道包括具有第一晶格常数的第一材料和耦合到 量子阱沟道，源结构包括具有第二晶格常数的第二材料，其中第二晶格常数不同于在量子阱沟道上施加应变的第一晶格常数。 可以描述和/或要求保护其他实施例。

    HIGH INDIUM CONTENT TRANSISTOR CHANNELS
    107.
    发明申请
    HIGH INDIUM CONTENT TRANSISTOR CHANNELS 审中-公开
    高含量晶体管通道

    公开(公告)号：US20120153352A1

    公开(公告)日：2012-06-21

    申请号：US12968905

    申请日：2010-12-15

    Applicant: Gilbert Dewey ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Benjamin Chu-Kung

    Inventor： Gilbert Dewey ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Benjamin Chu-Kung

    IPC: H01L29/778

    CPC classification number: H01L29/78696 ,  H01L29/20

    Abstract: The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the formation of high mobility transistor channels from high indium content alloys, wherein the high indium content transistor channels are achieved with a barrier layer that can substantially lattice match with the high indium content transistor channel.

    Abstract translation: 本公开内容涉及微电子晶体管制造领域，更具体地涉及从高铟含量合金形成高迁移率晶体管沟道，其中高铟含量晶体管沟道通过阻挡层实现，该阻挡层基本上可以与 高铟含量晶体管通道。

    Modulation-doped multi-gate devices
    109.
    发明授权
    Modulation-doped multi-gate devices 有权
    调制掺杂多栅极器件

    公开(公告)号：US08120063B2

    公开(公告)日：2012-02-21

    申请号：US12345489

    申请日：2008-12-29

    Applicant: Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

    Inventor： Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

    IPC: H01L29/267

    CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795

    Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.

    Abstract translation: 通常描述调制掺杂多栅极器件。 在一个示例中，设备包括具有表面的半导体衬底，耦合到半导体衬底的表面的一个或多个缓冲膜，耦合到该一个或多个缓冲膜的第一阻挡膜，耦合到第一 所述多栅极鳍片包括源极区域，漏极区域和多栅极器件的沟道区域，其中所述沟道区域设置在所述源极区域和所述漏极区域之间，间隔膜耦合到所述多栅极器件， 栅极鳍片以及耦合到间隔膜的掺杂膜。

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