公开(公告)号：US12206325B2

公开(公告)日：2025-01-21

申请号：US18135395

申请日：2023-04-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Thoan Nguyen ,  Nghia Nguyen ,  Viet Nguyen ,  Son Nguyen ,  Hien Lai ,  Phuong Nguyen

IPC: H02M3/07

Abstract: In one example, a system comprises a plurality of charge pump units connected in parallel to receive an input voltage and to generate an output voltage greater than the input voltage and a pumping controller to provide a pumping signal to a first charge pump unit of the plurality of charge pump units and to provide sequentially delayed versions of the pumping signal to the other charge pump units of the plurality of charge pump units.

公开(公告)号：US20240389319A1

公开(公告)日：2024-11-21

申请号：US18228414

申请日：2023-07-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/40

Abstract: A memory device includes a SOI substrate comprising bulk silicon, an insulation layer vertically over the bulk silicon, and a silicon layer vertically over the insulation layer. A memory cell includes source and drain regions formed in the bulk silicon with a channel region of the bulk silicon extending therebetween, and a floating gate which includes a first portion of the silicon layer disposed vertically over and insulated from a first portion of the channel region by the insulation layer. The first portion of the silicon layer is epitaxially thickened or a layer of polysilicon is formed on the first portion of the silicon layer. A select gate is disposed vertically over and insulated from a second portion of the channel region. A control gate is disposed vertically over and insulated from the floating gate. An erase gate is disposed vertically over and insulated from the source region.

公开(公告)号：US20240338144A1

公开(公告)日：2024-10-10

申请号：US18212066

申请日：2023-06-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEPHEN TRINH ,  HOA VU ,  STANLEY HONG ,  THUAN VU

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/062 ,  G06F3/0679 ,  G11C16/08

Abstract: Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.

公开(公告)号：US20240257880A1

公开(公告)日：2024-08-01

申请号：US18104228

申请日：2023-01-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Louisa Schneider ,  Xian Liu ,  Steven Lemke ,  Parviz Ghazavi ,  Jinho Kim ,  Henry A. Om'Mani ,  Hieu Van Tran ,  Nhan Do

IPC: G11C16/16 ,  H01L23/48 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27

CPC classification number: G11C16/16 ,  H01L23/481 ,  H01L29/42328 ,  H10B41/10 ,  H10B41/27

Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

公开(公告)号：US20240220154A1

公开(公告)日：2024-07-04

申请号：US18604884

申请日：2024-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G06F3/06 ,  G06N3/065 ,  G11C7/10 ,  G11C7/16 ,  G11C11/54 ,  G11C27/00

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06N3/065 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/54 ,  G11C27/005

Abstract: Numerous embodiments of an array of non-volatile memory cells are disclosed herein. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns; wherein in a first mode, the array stores digital data; and wherein in a second mode, the array stores analog data.

公开(公告)号：US12020762B2

公开(公告)日：2024-06-25

申请号：US17576754

申请日：2022-01-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Yuri Tkachev ,  Jinho Kim ,  Cynthia Fung ,  Gilles Festes ,  Bernard Bertello ,  Parviz Ghazavi ,  Bruno Villard ,  Jean Francois Thiery ,  Catherine Decobert ,  Serguei Jourba ,  Fan Luo ,  Latt Tee ,  Nhan Do

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G11C2029/5006

Abstract: A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1. A second read operation is performed to determine a second number N2 of the memory cells having a read current not exceeding a target read current RC2. The target read current RC2 is equal to the lowest read current RC1 plus a predetermined current value. The die is determined to be acceptable if the second number N2 is determined to exceed the first number N1 plus a predetermined number. The die is determined to be defective if the second number N2 is determined not to exceed the first number N1 plus the predetermined number.

公开(公告)号：US11989440B2

公开(公告)日：2024-05-21

申请号：US17519241

申请日：2021-11-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G11C7/16 ,  G06F3/06 ,  G06N3/065 ,  G11C7/10 ,  G11C11/54 ,  G11C27/00

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06N3/065 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/54 ,  G11C27/005

Abstract: Numerous embodiments of a hybrid memory system are disclosed. The hybrid memory can store weight data in an array in analog form when used in an analog neural memory system or in digital form when used in a digital neural memory system. Input circuitry and output circuitry are capable of supporting both forms of weight data.

公开(公告)号：US20240112003A1

公开(公告)日：2024-04-04

申请号：US18077993

申请日：2022-12-08

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  NGHIA LE ,  HIEN PHAM

IPC: G06N3/063 ,  G06F5/01 ,  G06F7/501

CPC classification number: G06N3/063 ,  G06F5/01 ,  G06F7/501

Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.

公开(公告)号：US11935594B2

公开(公告)日：2024-03-19

申请号：US17672617

申请日：2022-02-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC: G11C16/08 ,  G06N3/065 ,  G11C11/54

CPC classification number: G11C16/08 ,  G06N3/065 ,  G11C11/54

Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.

公开(公告)号：US11875852B2

公开(公告)日：2024-01-16

申请号：US17140924

申请日：2021-01-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Nhan Do ,  Mark Reiten

IPC: G11C7/12 ,  G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation while maintaining accuracy in the operation.