公开(公告)号：US20170083065A1

公开(公告)日：2017-03-23

申请号：US14862044

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Manish Arora ,  Yasuko Eckert ,  Indrani Paul

IPC: G06F1/20 ,  G06F1/32 ,  G06T1/20

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3024 ,  G06F11/3058

Abstract: A three-dimensional (3-D) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. The controller selectively throttles the one or more of the plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of processor cores.

公开(公告)号：US09286948B2

公开(公告)日：2016-03-15

申请号：US13941791

申请日：2013-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Nuwan S. Jayasena ,  James M. O'Connor ,  Yasuko Eckert

IPC: G11C5/02 ,  G06F12/02 ,  G06F12/10

CPC classification number: G11C5/025 ,  G06F3/0608 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/10 ,  G06F17/30477 ,  G06F17/30982 ,  G06F2212/60 ,  G11C5/02 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The set of one or more logic dies includes a query controller and a memory controller. The memory controller is coupleable to at least one device external to the stacked-die memory device. The query controller is to perform a query operation on data stored in the memory cell circuitry responsive to a query command received from the external device.

Abstract translation: 集成电路（IC）封装包括堆叠式存储器件。 堆叠式存储器件包括一组实现存储器单元电路的一个或多个堆叠存储器管芯。 堆叠裸片存储器件还包括电耦合到存储单元电路的一组或多个逻辑管芯。 一个或多个逻辑管芯的集合包括查询控制器和存储器控制器。 存储器控制器可耦合到堆叠式存储器件外部的至少一个器件。 查询控制器响应于从外部设备接收的查询命令，对存储在存储单元电路中的数据执行查询操作。

公开(公告)号：US09128856B2

公开(公告)日：2015-09-08

申请号：US13854724

申请日：2013-04-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna Thottethodi ,  Yasuko Eckert ,  Srilatha Manne

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0888 ,  G06F12/0893

Abstract: A cache memory receives a request to perform a write operation. The request specifies an address. A first determination is made that the cache memory does not include a cache line corresponding to the address. A second determination is made that the address is between a previous value of a stack pointer and a current value of the stack pointer. A third determination is made that a write history indicator is set to a specified value. The write operation is performed in the cache memory without waiting for a cache fill corresponding to the address to be performed, in response to the first, second, and third determinations.

Abstract translation: 缓存存储器接收执行写入操作的请求。 请求指定一个地址。 首先确定高速缓冲存储器不包括与该地址对应的高速缓存行。 第二个确定是地址在堆栈指针的先前值和堆栈指针的当前值之间。 第三个确定写入历史指示符被设置为指定值。 响应于第一，第二和第三确定，在高速缓冲存储器中执行写入操作，而不等待与要执行的地址相对应的高速缓存填充。

公开(公告)号：US09075730B2

公开(公告)日：2015-07-07

申请号：US13725011

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh ,  James M. O'Connor ,  Yasuko Eckert ,  Bradford M. Beckmann

IPC: G06F12/08

CPC classification number: G06F12/0871 ,  G06F12/0848

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括缓存和用于存储器请求的一个或多个源。 响应于接收到分配第一类型的数据的请求，高速缓存控制器响应于确定未达到高速缓存中允许的第一类型的数据量的极限而分配缓存中的数据。 控制器维护存储在高速缓存中的第一类型的数据的量和位置信息。 此外，可以用指定用于存储给定类型的数据的每个分区对高速缓存进行分区。 第一类型的数据的分配至少依赖于第一分区的可用性和第二分区中第一类型的数据量的限制。

公开(公告)号：US20150067305A1

公开(公告)日：2015-03-05

申请号：US14015282

申请日：2013-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Srilatha Manne

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0875

Abstract: A system and method for efficient predicting and processing of memory access dependencies. A computing system includes control logic that marks a detected load instruction as a first type responsive to predicting the load instruction has high locality and is a candidate for store-to-load (STL) data forwarding. The control logic marks the detected load instruction as a second type responsive to predicting the load instruction has low locality and is not a candidate for STL data forwarding. The control logic processes a load instruction marked as the first type as if the load instruction is dependent on an older store operation. The control logic processes a load instruction marked as the second type as if the load instruction is independent on any older store operation.

Abstract translation: 一种用于有效预测和处理内存访问依赖关系的系统和方法。 计算系统包括控制逻辑，其将检测到的加载指令标记为响应于预测加载指令具有高局部性并且是存储到加载（STL）数据转发的候选者的第一类型。 控制逻辑将检测到的加载指令标记为响应于预测加载指令具有低局部性而不是STL数据转发的候选的第二类型。 控制逻辑处理标记为第一类型的加载指令，就像加载指令取决于较旧的存储操作一样。 控制逻辑处理标记为第二类型的加载指令，就像加载指令独立于任何较旧的存储操作一样。

公开(公告)号：US20150067264A1

公开(公告)日：2015-03-05

申请号：US14012475

申请日：2013-08-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Syed Ali Jafri ,  Srilatha Manne ,  Gabriel Loh

IPC: G06F12/08

CPC classification number: G06F12/126 ,  Y02D10/13

Abstract: In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.

Abstract translation: 在一些实施例中，管理高速缓存存储器的方法包括基于高速缓存行之间的相关性来识别高速缓存存储器中的一组高速缓存行。 该方法还包括跟踪来自高速缓存存储器的组中的高速缓存行的移除，并且响应于确定与高速缓冲存储器中的组中的高速缓存行的逐出的标准被选择一个或多个（例如全部） 组中的剩余高速缓存行被驱逐。

公开(公告)号：US20150016172A1

公开(公告)日：2015-01-15

申请号：US13941791

申请日：2013-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Nuwan S. Jayasena ,  James M. O'Connor ,  Yasuko Eckert

IPC: G11C5/02

CPC classification number: G11C5/025 ,  G06F3/0608 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/10 ,  G06F17/30477 ,  G06F17/30982 ,  G06F2212/60 ,  G11C5/02 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The set of one or more logic dies includes a query controller and a memory controller. The memory controller is coupleable to at least one device external to the stacked-die memory device. The query controller is to perform a query operation on data stored in the memory cell circuitry responsive to a query command received from the external device.

Abstract translation: 集成电路（IC）封装包括堆叠式存储器件。 堆叠式存储器件包括一组实现存储器单元电路的一个或多个堆叠存储器管芯。 堆叠裸片存储器件还包括电耦合到存储单元电路的一组或多个逻辑管芯。 一个或多个逻辑管芯的集合包括查询控制器和存储器控制器。 存储器控制器可耦合到堆叠式存储器件外部的至少一个器件。 查询控制器响应于从外部设备接收的查询命令，对存储在存储单元电路中的数据执行查询操作。

公开(公告)号：US08935472B2

公开(公告)日：2015-01-13

申请号：US13723294

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna Thottethodi ,  Gabriel Loh ,  Mauricio Breternitz ,  James O'Connor ,  Yasuko Eckert

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F2212/601 ,  Y02D10/13

Abstract: A data processing device is provided that includes an array of working memory banks and an associated processing engine. The working memory bank array is configured with at least one independently activatable memory bank. A dirty data counter (DDC) is associated with the independently activatable memory bank and is configured to reflect a count of dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank. The DDC is configured to selectively decrement the count of dirty data upon the reactivation of the independently activatable memory bank in connection with a transient state. In the transient state, each dirty data access by the processing engine to the reactivated memory bank is also conducted with respect to another memory bank of the array. Upon a condition that dirty data is found in the other memory bank, the count of dirty data is decremented.

Abstract translation: 提供了一种数据处理装置，其包括工作存储器组和相关处理引擎的阵列。 工作存储器阵列配置有至少一个可独立激活的存储体。 脏数据计数器（DDC）与可独立激活的存储体相关联，并且被配置为反映从可独立激活的存储体选择性地去激活时从可独立激活的存储体组迁移的脏数据的计数。 DDC被配置为在与暂时状态相关联的可独立激活的存储体的重新激活时选择性地减少脏数据的计数。 在过渡状态下，处理引擎对重新激活的存储体的每个脏数据访问也相对于阵列的另一存储体进行。 在另一个存储体中发现脏数据的情况下，脏数据的计数减少。

公开(公告)号：US20240329984A1

公开(公告)日：2024-10-03

申请号：US18128963

申请日：2023-03-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Vadim Vadimovich Nikiforov ,  Gabriel H. Loh ,  Bradford Beckmann

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30109

Abstract: An electronic device includes processing circuitry that executes a lookup table (LUT) vector instruction. Executing the lookup table vector instruction causes the processing circuitry to acquire a set of reference values by using each input value from an input vector as an index to acquire a reference value from a reference vector. The processing circuitry then provides the set of reference values for one or more subsequent operations. The processing circuitry can also use the set of reference values for controlling vector elements from among a set of vector elements for which a vector operation is performed.

公开(公告)号：US20240264900A1

公开(公告)日：2024-08-08

申请号：US18625417

申请日：2024-04-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Divya Madapusi Srinivas Prasad ,  Sudhanva Gurumurthi ,  Yasuko Eckert ,  Jeffrey Richard Rearick ,  Sankaranarayanan Gurumurthy ,  Amitabh Mehra ,  Shidhartha Das ,  Alex W. Schaefer ,  Vikram Ramachandra ,  Vilas Sridharan

IPC: G06F11/07 ,  G06F1/30

CPC classification number: G06F11/0793 ,  G06F11/07 ,  G06F1/30 ,  G06F11/0721

Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.