公开(公告)号：US20200176419A1

公开(公告)日：2020-06-04

申请号：US16503806

申请日：2019-07-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L21/768 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip including a reconstituted chip-level back endo of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US20170323883A1

公开(公告)日：2017-11-09

申请号：US15658670

申请日：2017-07-25

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Vidhya Ramachandran ,  Kunzhong Hu ,  Mengzhi Pang ,  Chonghua Zhong

IPC: H01L27/06 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16 ,  H01L21/77 ,  H01L49/02

CPC classification number: H01L27/0641 ,  H01L21/77 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L28/10 ,  H01L28/40 ,  H01L28/90 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

公开(公告)号：US09679801B2

公开(公告)日：2017-06-13

申请号：US14730171

申请日：2015-06-03

Applicant: Apple Inc.

Inventor： Kwan-Yu Lai ,  Jun Zhai ,  Kunzhong Hu ,  Flynn P. Carson

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/768 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 μm thick.

公开(公告)号：US20160300823A1

公开(公告)日：2016-10-13

申请号：US15184554

申请日：2016-06-16

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Chonghua Zhong

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: In some embodiments, a semiconductor device package on package assembly may include a first package, a second package, and a third package. The first package may include a first surface, a second surface, a first die, and a first set of electrical conductors. The first set of electrical conductors may be configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface, and a local memory module. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The third package may include a fifth surface and a sixth surface, and a main memory module. The fifth surface may be coupled to the fourth surface. The third package may be electrically coupled to the first package and/or the second package.

Abstract translation: 在一些实施例中，封装组件上的半导体器件封装可以包括第一封装，第二封装和第三封装。 第一封装可以包括第一表面，第二表面，第一管芯和第一组电导体。 第一组电导体可以被配置为将封装电连接在封装组件上。 第二包装可以包括第三表面和第四表面以及本地存储器模块。 第三表面可以联接到第二表面。 第一封装可以电耦合到第二封装。 第三包装可以包括第五表面和第六表面，以及主存储器模块。 第五表面可以联接到第四表面。 第三封装可以电耦合到第一封装和/或第二封装。

公开(公告)号：US20160300813A1

公开(公告)日：2016-10-13

申请号：US14680539

申请日：2015-04-07

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Chonghua Zhong ,  Mengzhi Pang ,  Se Young Yang

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/83

Abstract: Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) formed directly on a top die, and a bottom die mounted on a back surface of the RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，包装包括直接形成在顶模上的再分配层（RDL）和安装在RDL的后表面上的底模。

公开(公告)号：US20150364422A1

公开(公告)日：2015-12-17

申请号：US14497495

申请日：2014-09-26

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L24/03 ,  H01L21/563 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/16227 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2225/1035 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device package includes a logic die coupled to a memory die in a side-by-side configuration on a redistribution layer (e.g., the logic die and the memory die are substantially adjacent). A silicon bridge may be used to interconnect the logic die and the memory die. The silicon bridge may be positioned between the die and the redistribution layer. The silicon bridge and the redistribution layer may be coupled to the lower (active) surfaces of the logic die and the memory die. The package may be formed using a wafer level process that forms a plurality of packages simultaneously.

Abstract translation: 半导体器件封装包括在再分配层（例如，逻辑管芯和存储器管芯基本相邻）上并排配置地耦合到存储器管芯的逻辑管芯。 硅桥可以用于互连逻辑管芯和存储管芯。 硅桥可以位于管芯和再分配层之间。 硅桥和再分配层可以耦合到逻辑管芯和存储管芯的下（有源）表面。 可以使用同时形成多个包装的晶片级处理来形成封装。