公开(公告)号：US6054808A

公开(公告)日：2000-04-25

申请号：US237394

申请日：1999-01-26

Applicant: Charles M. Watkins ,  David A. Cathey

Inventor： Charles M. Watkins ,  David A. Cathey

IPC: H01J9/20 ,  H01J29/08 ,  H01J29/94 ,  H01J1/72

CPC classification number: H01J9/20 ,  H01J29/085 ,  H01J29/94

Abstract: A field emission display has an anode with a grille made at least in part of a getter material. The grille defines regions that are coated with phosphor to form pixels, and also getters free molecules within a sealed display. The getter material can alternatively be formed directly on at least a part of the grille, or over the grille on an intermediate layer.

公开(公告)号：US6033278A

公开(公告)日：2000-03-07

申请号：US127014

申请日：1998-07-31

Applicant: Charles M. Watkins ,  David A. Cathey

Inventor： Charles M. Watkins ,  David A. Cathey

IPC: H01J7/18 ,  H01J9/38 ,  H01J29/94

CPC classification number: H01J9/38 ,  H01J29/94 ,  H01J7/186 ,  H01J2209/012 ,  H01J2209/385 ,  H01J2329/00

Abstract: The present invention provides an FED with a getter material deposited and activated on the substrates of the faceplate and the baseplate of the FED. In one embodiment of the invention, a large FED includes a faceplate, a baseplate, and an unactivated non-evaporable getter material. The faceplate has a transparent substrate with an inner surface, and a cathodoluminescent material disposed on a portion of the inner surface. The baseplate has a base substrate with a first surface and an emitter array formed on the first surface. The baseplate and the faceplate are coupled together to form a sealed vacuum space in which the inner surface and the first surface are juxtaposed to one another in a spaced-apart relationship across a vacuum gap. The unactivated non-evaporating getter material is deposited directly on the inner surface and/or the first surface. The unactivated non-evaporating getter material may alternatively be deposited on a thin film of bonding material that is disposed on the inner surface and/or the first surface.

公开(公告)号：US6010917A

公开(公告)日：2000-01-04

申请号：US725646

申请日：1996-10-15

Applicant: James J. Alwan ,  Kevin Tjaden ,  David A. Cathey

Inventor： James J. Alwan ,  Kevin Tjaden ,  David A. Cathey

IPC: H01L21/00

CPC classification number: H01J31/127 ,  H01J29/467 ,  H01J3/022 ,  H01J9/148 ,  H01J2203/0228 ,  H01J2203/0232 ,  H01J2329/4626 ,  H01J2329/463

Abstract: A method for fabricating microelectronic deices in which an interconnect layer is electrically isolated from large protuberances that project from a lower conductive layer to a desired endpoint of a chemical-mechanical planarization process. The lower conductive layer is covered with an insulating material to form an insulator layer that generally follows the contour of the lower conductive layer and any large protuberances. A highly conductive interconnect material is then deposited over the insulator layer to form an interconnect layer that generally follows the contour of the insulator layer. The interconnect layer may be deposited directly on the insulator layer, or it may be deposited on an intermediate layer between the interconnect layer and the insulator layer. After the upper conductive layer is deposited, the insulator layer and the upper conductive layer are planarized with a chemical-mechanical planarization process to a desired endpoint.

Abstract translation: 一种用于制造微电子器件的方法，其中互连层与从下导电层突出到化学机械平面化工艺的期望端点的大突起电隔离。 下导电层被绝缘材料覆盖以形成通常遵循下导电层和任何大突起的轮廓的绝缘体层。 然后将高度导电的互连材料沉积在绝缘体层上，以形成大致遵循绝缘体层的轮廓的互连层。 互连层可以直接沉积在绝缘体层上，或者它可以沉积在互连层和绝缘体层之间的中间层上。 在沉积上导电层之后，通过化学机械平面化工艺将绝缘体层和上导电层平坦化成期望的端点。

公开(公告)号：US5817373A

公开(公告)日：1998-10-06

申请号：US764756

申请日：1996-12-12

Applicant: David A. Cathey ,  Kevin Tjaden ,  James J. Alwan

Inventor： David A. Cathey ,  Kevin Tjaden ,  James J. Alwan

IPC: H01J9/02 ,  B05D1/06 ,  B05D1/32 ,  C03C25/06

CPC classification number: H01J9/025

Abstract: A substrate is placed on a charging surface, to which a first voltage is applied. Etch-resistant dry particles are placed in a cup in a nozzle to which a second voltage, less than the first voltage, is applied. A carrier gas is directed through the nozzle, which projects the dry particles out of the nozzle toward the substrate. The particles pick up a charge from the potential applied to the nozzle and are electrostatically attracted to the substrate. The particles adhere to the substrate, where they form an etch mask. The substrate is etched and the particles are removed. Emitter tips for a field emission display may be formed in the substrate.

Abstract translation: 将基板放置在施加第一电压的充电表面上。 将耐蚀刻干燥颗粒放置在喷嘴中的杯中，其中施加小于第一电压的第二电压。 载气被引导通过喷嘴，其将干燥颗粒从喷嘴向衬底投射。 颗粒从施加到喷嘴的电位拾取电荷，并被静电吸引到基板上。 颗粒粘附到基底上，在那里它们形成蚀刻掩模。 蚀刻基板并除去颗粒。 用于场致发射显示器的发射极尖端可以形成在衬底中。

公开(公告)号：US5801103A

公开(公告)日：1998-09-01

申请号：US566513

申请日：1995-12-04

Applicant: Robert T. Rasmussen ,  Surjit S. Chadha ,  David A. Cathey

Inventor： Robert T. Rasmussen ,  Surjit S. Chadha ,  David A. Cathey

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/302

CPC classification number: H01L21/31111 ,  H01L21/02071 ,  Y10S148/051 ,  Y10T428/24802

Abstract: The present invention is directed to a novel etching process for a semiconductor material which inhibits corrosion of metal comprised of pretreating the material, preferably with a surfactant, and then exposing the material to a mixture comprising a buffered oxide etch.

公开(公告)号：US5772488A

公开(公告)日：1998-06-30

申请号：US543819

申请日：1995-10-16

Applicant: David A. Cathey ,  Surjit S. Chadha ,  Behnam Moradi

Inventor： David A. Cathey ,  Surjit S. Chadha ,  Behnam Moradi

IPC: H01J1/62 ,  H01J9/02 ,  H01J63/04

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: According to one aspect of the invention, a field emission display is provided comprising: an anode; a phosphor screen located on the anode; a cathode; an evacuated space between the anode and the cathode; an emitter located on the cathode opposite the phosphor; wherein the emitter comprises an electropositive element both in a body of the emitter and on a surface of the emitter. According to another aspect of the invention a process for manufacturing an FED is provided comprising the steps of: forming an emitter comprising an electropositive element in the body of the tip; positioning the emitter in opposing relation to a phosphor display screen; creating an evacuated space between the emitter tip and the phosphor display screen; and causing the electropositive element to migrate to the an emission surface of the emitter.

Abstract translation: 根据本发明的一个方面，提供一种场发射显示器，包括：阳极; 位于阳极上的荧光屏; 阴极 阳极和阴极之间的抽空空间; 位于与磷光体相对的阴极上的发射极; 其中所述发射器包括在所述发射体的主体和所述发射极的表面上的正电极元件。 根据本发明的另一方面，提供了一种用于制造FED的方法，包括以下步骤：在尖端的主体中形成包含正电荷元件的发射器; 将发射器定位成与荧光体显示屏相对的关系; 在发射极尖端和荧光体显示屏之间产生抽空空间; 并使正电荷元件迁移到发射体的发射表面。

公开(公告)号：US5753130A

公开(公告)日：1998-05-19

申请号：US665620

申请日：1996-06-18

Applicant: David A. Cathey ,  Kevin Tjaden

Inventor： David A. Cathey ,  Kevin Tjaden

IPC: H01J9/02 ,  H01J9/00

CPC classification number: H01J9/025 ,  H01J2201/30403

Abstract: A method for fabricating sharp asperities. A substrate is provided which has a mask layer disposed thereon, and a layer of micro-spheres is disposed superjacent the mask layer. The micro-spheres are for patterning the mask layer. Portions of the mask layer are selectively removed, thereby forming circular masks. The substrate is isotropically etched, thereby creating sharp asperities.

Abstract translation: 一种制造尖锐凹凸的方法。 提供了具有设置在其上的掩模层的基板，并且在该掩模层的上方布置一层微球。 微球用于图案化掩模层。 选择性地去除掩模层的一部分，从而形成圆形掩模。 基板被各向同性地蚀刻，从而产生尖锐的凹凸。

公开(公告)号：USRE35420E

公开(公告)日：1997-01-07

申请号：US491627

申请日：1995-06-19

Applicant: David A. Cathey ,  Mark E. Tuttle ,  Tyler A. Lowrey

Inventor： David A. Cathey ,  Mark E. Tuttle ,  Tyler A. Lowrey

IPC: H01L21/02 ,  H01L21/334 ,  H01C21/28

CPC classification number: H01L28/84 ,  H01L29/66181

Abstract: A method of increasing capacitance by surface roughening in semiconductor wafer processing includes the following steps: a) applying a first layer of material atop a substrate thereby defining an exposed surface; b) incontinuously adhering discrete solid particles to the first layer exposed surface to roughen the exposed surface; and c) applying a second layer of material atop the first layer and adhered solid particles to define an outer surface, the particles adhered to the first layer reducing roughness into the outer surface thereby increasing its surface area and accordingly capacitance of the second layer in the final wafer structure.

Abstract translation: 通过在半导体晶片处理中通过表面粗糙度增加电容的方法包括以下步骤：a）在基板顶部施加第一层材料，从而限定暴露的表面; b）不连续地将离散的固体颗粒粘附到第一层暴露表面以使暴露的表面粗糙; 以及c）在第一层顶部施加第二层材料并粘附固体颗粒以限定外表面，所述粘附到第一层的颗粒将粗糙度减小到外表面中，从而增加其表面积，从而增加其中的第二层的电容 最终的晶圆结构。

公开(公告)号：US5486126A

公开(公告)日：1996-01-23

申请号：US349091

申请日：1994-11-18

Applicant: David A. Cathey ,  James J. Hofmann ,  Danny Dynka ,  Darryl M. Stansbury

Inventor： David A. Cathey ,  James J. Hofmann ,  Danny Dynka ,  Darryl M. Stansbury

IPC: G09F9/30 ,  G09F9/313 ,  H01J9/18 ,  H01J9/24 ,  H01J29/02 ,  H01J29/86 ,  H01J31/12

CPC classification number: H01J9/242 ,  H01J29/028 ,  H01J29/864 ,  H01J31/123 ,  H01J31/127 ,  H01J9/185 ,  H01J2329/8625 ,  H01J2329/863 ,  H01J2329/8635 ,  H01J2329/864 ,  H01J2329/8645 ,  H01J2329/866 ,  Y10T29/4981

Abstract: A process is provided for forming spacers useful in large area displays. The process comprises steps of: forming bundles comprising fiber strands which are held together with a binder; slicing the bundles into slices; adhering the slices on an electrode plate of the display; and removing the binder.

Abstract translation: 提供用于形成用于大面积显示器的间隔物的方法。 该方法包括以下步骤：形成包含与粘合剂保持在一起的纤维束的束; 将束切成片; 将切片粘附在显示器的电极板上; 并移除粘合剂。

公开(公告)号：US5403435A

公开(公告)日：1995-04-04

申请号：US195950

申请日：1994-02-14

Applicant: David A. Cathey ,  J. Brett Rolfson

Inventor： David A. Cathey ,  J. Brett Rolfson

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  B44C1/22 ,  C23F1/00 ,  H01L21/44

CPC classification number: H01L28/40 ,  H01L21/0274 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/948 ,  Y10S438/978

Abstract: An improved process for selectively etching integrated circuit devices having deep trenches or troughs or elevated features with re-entrant profiles is disclosed. The process is capable of producing photoresist patterns having line and space dimensions which are less than 3 microns. Such patterns may be employed to produce high-resolution etched patterns within the functional layers comprising those circuits. The process proceeds without the formation of unwanted residual photoresist material in deep trenches and troughs and in recesses along the sidewalls of raised features having re-entrant sidewall profiles. No auxiliary, critical-dimension-shrinking etch step is required to remove such residual photoresist in those locations. The process is particularly useful for in-process integrated circuit having either a plurality of elevated features or a plurality of trenches or troughs, in combination with at least one conductivity-providing layer, which covers the raised features or lines the trenches or troughs. The process involves forming an etch mask pattern on the in-process circuit using negative photoresist as the mask material, with the pattern covering certain portions of the conductivity-providing layer and exposing other portions of the conductivity-providing layer. The exposed portions of the conductivity-providing layer are then etched.

Abstract translation: 公开了一种改进的方法，用于选择性地蚀刻具有深槽或槽的集成电路器件或具有入口轮廓的升高的特征。 该方法能够产生具有小于3微米的线和空间尺寸的光致抗蚀剂图案。 可以使用这样的图案来在包括那些电路的功能层内产生高分辨率蚀刻图案。 该过程继续进行，而不会在深沟槽和槽中形成不需要的剩余光致抗蚀剂材料，并且沿着具有凹入侧壁轮廓的凸起特征的侧壁的凹部中形成。 不需要辅助的临界尺寸缩小蚀刻步骤来去除这些位置处的这种残余光致抗蚀剂。 该过程对于具有多个升高的​​特征或多个沟槽或槽的进程中集成电路特别有用，该至少一个电导率提供层与覆盖凸起的特征​​或者沟槽或槽的线组合。 该工艺包括在负极光致抗蚀剂作为掩模材料的过程中电路上形成蚀刻掩模图案，图案覆盖导电性提供层的某些部分并暴露导电性提供层的其它部分。 然后蚀刻导电性提供层的暴露部分。