公开(公告)号：US08531002B2

公开(公告)日：2013-09-10

申请号：US12899384

申请日：2010-10-06

申请人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

发明人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

IPC分类号： H01L27/08

CPC分类号： H01L23/5227 ,  C23C28/023 ,  C25D5/022 ,  C25D7/123 ,  C25D17/001 ,  H01L27/0207 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

摘要翻译： 用于直接在半导体集成电路之上晶圆级制造高值电感器的装置和方法。 该装置和方法包括制造包括多个骰子的半导体晶片，每个骰子包括电源电路和开关节点。 一旦制造晶片，则分别将多个电感器直接制造在晶片上的多个晶片上。 每个电感器通过在形成在晶片上的互连电介质层上形成多个磁芯电感器构件来制造。 然后在每个管芯上方的多个磁芯电感器部件上形成绝缘层，然后形成电感器线圈。 分别在多个电感器上形成电镀磁性层，以提高结构的磁导率和电感。

公开(公告)号：US20130174117A1

公开(公告)日：2013-07-04

申请号：US13339880

申请日：2011-12-29

申请人： Christina Watters ,  Peter Johnson ,  Robert S. Baker

发明人： Christina Watters ,  Peter Johnson ,  Robert S. Baker

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F11/3664 ,  G06F8/71

摘要： System and method for forming a cloud appliance. The system includes a management server, an artifact repository, a continuous integration server, and build managers. The management server includes source code and a project script for forming the cloud appliance. The artifact repository stores artifacts required to build the cloud appliance and artifacts that comprise the built cloud appliance. The continuous integration server manages a build process, unit test process, and deployment process based on the project script. The build managers build the source code for customizing the virtual machine and store the built source code as the second artifacts in the artifact repository. The continuous integration server instantiates the virtual machine from template and customizes the virtual machine to form a customized virtual machine using the artifacts specified in the project script, a customization process for each of the artifacts based on a type of the artifact.

摘要翻译： 用于形成云设备的系统和方法。 该系统包括管理服务器，工件存储库，持续集成服务器和构建管理器。 管理服务器包括用于形成云设备的源代码和项目脚本。 工件存储库存储构建云设备所需的工件，以及组成构建的云设备的工件。 持续集成服务器根据项目脚本管理构建过程，单元测试过程和部署过程。 构建管理器构建用于自定义虚拟机的源代码，并将构建的源代码作为第二个工件存储在工件存储库中。 连续集成服务器从模板中实例化虚拟机，并使用项目脚本中指定的工件，基于工件类型的每个工件的自定义过程来自定义虚拟机以形成自定义虚拟机。

公开(公告)号：US20130140654A1

公开(公告)日：2013-06-06

申请号：US13309773

申请日：2011-12-02

申请人： Steven Adler ,  Peter Johnson ,  Ira Oaktree Wygant

发明人： Steven Adler ,  Peter Johnson ,  Ira Oaktree Wygant

IPC分类号： H01L29/84 ,  H01L21/02

CPC分类号： H01L29/84 ,  B06B1/0292 ,  H01L29/66007

摘要： A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves.

摘要翻译： 具有能够在空腔上振动的导电结构的电容式微加工超声波换能器（CMUT）具有形成在空腔的底表面中的多个通气孔。 通气孔消除了由于大气压力导致的CMUT膜的挠曲，这进一步允许CMUT接收和传输低频超声波。

公开(公告)号：US20130049916A1

公开(公告)日：2013-02-28

申请号：US13218682

申请日：2011-08-26

申请人： Ann Gabrys ,  William French ,  Peter J. Hopper ,  Dok Won Lee ,  Peter Johnson

发明人： Ann Gabrys ,  William French ,  Peter J. Hopper ,  Dok Won Lee ,  Peter Johnson

IPC分类号： H01F5/00 ,  H01L21/02

CPC分类号： H01L23/5227 ,  H01F2027/2809 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/30107 ,  Y10T29/41 ,  H01L2924/00014 ,  H01L2924/00

摘要： A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.

摘要翻译： 电流管芯具有信号结构和变压器结构，其为高电压管芯和低压管芯提供电流隔离的信号和功率路径，这两者都由电流管芯物理地支撑并电连接到信号和变压器结构 的电镀模具。

公开(公告)号：US08378776B1

公开(公告)日：2013-02-19

申请号：US13218682

申请日：2011-08-26

申请人： Ann Gabrys ,  William French ,  Peter J. Hopper ,  Dok Won Lee ,  Peter Johnson

发明人： Ann Gabrys ,  William French ,  Peter J. Hopper ,  Dok Won Lee ,  Peter Johnson

IPC分类号： H01F5/00 ,  H01F27/28 ,  H01F27/29 ,  H01L29/66 ,  H01L27/08 ,  H01L21/02 ,  H01L27/06

CPC分类号： H01L23/5227 ,  H01F2027/2809 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/30107 ,  Y10T29/41 ,  H01L2924/00014 ,  H01L2924/00

摘要： A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.

摘要翻译： 电流管芯具有信号结构和变压器结构，其为高电压管芯和低压管芯提供电流隔离的信号和功率路径，这两者都由电流管芯物理地支撑并电连接到信号和变压器结构 的电镀模具。

公开(公告)号：US08378460B2

公开(公告)日：2013-02-19

申请号：US12978492

申请日：2010-12-24

申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

IPC分类号： H01L23/48 ,  H01L23/544 ,  H01L21/66

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/0802 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.

摘要翻译： 在每个晶片被形成为包括暴露高精度电路的电路内部的可调节电路元件的开口的过程中，每个具有多个高精度电路和相应的微调控制电路的多个晶片被批量修整。 高精度电路和微调控制电路在修整阶段通过沿着锯木街道行进的金属轨迹进行电激活。 该方法将晶片接触结构连接到每个晶片以电激活金属迹线。 该方法将具有晶片接触结构的晶片放置在当高精度电路的实际输出电压与高精度电路的预测输出电压不匹配时，暴露的可调节电路元件被电镀或阳极化的解决方案中。

公开(公告)号：US08324006B1

公开(公告)日：2012-12-04

申请号：US12589754

申请日：2009-10-28

申请人： Steven J. Adler ,  Peter Johnson ,  Ira Wygant

发明人： Steven J. Adler ,  Peter Johnson ,  Ira Wygant

IPC分类号： H01H9/00 ,  H01L21/449

CPC分类号： B06B1/0292

摘要： A method includes forming first isolation trenches in a first side of a first semiconductor-on-insulator (SOI) structure to electrically isolate multiple portions of the first SOI structure from each other. The method also includes bonding a second SOI structure to the first SOI structure to form multiple cavities between the SOI structures. The method further includes forming conductive plugs through a second side of the first SOI structure and forming second isolation trenches in the second side of the first SOI structure around the conductive plugs. In addition, the method includes removing portions of the second SOI structure to leave a membrane bonded to the first SOI structure. The isolated portions of the first SOI structure, the cavities, and the membrane form multiple capacitive micromachined ultrasonic transducer (CMUT) elements. Each CMUT element is formed in one of the isolated portions of the first SOI structure and includes multiple CMUT cells.

摘要翻译： 一种方法包括在第一绝缘体绝缘体（SOI）结构的第一侧中形成第一隔离沟槽，以将第一SOI结构的多个部分彼此电隔离。 该方法还包括将第二SOI结构接合到第一SOI结构以在SOI结构之间形成多个空腔。 该方法还包括通过第一SOI结构的第二侧形成导电插塞，并在导电插塞周围的第一SOI结构的第二侧形成第二隔离沟槽。 此外，该方法包括去除第二SOI结构的部分以留下结合到第一SOI结构的膜。 第一SOI结构，空腔和膜的隔离部分形成多个电容微加工超声换能器（CMUT）元件。 每个CMUT元件形成在第一SOI结构的隔离部分之一中，并且包括多个CMUT单元。

公开(公告)号：US08048704B2

公开(公告)日：2011-11-01

申请号：US12750145

申请日：2010-03-30

申请人： Peter Smeys ,  Peter Johnson

发明人： Peter Smeys ,  Peter Johnson

IPC分类号： H01L33/12 ,  H01L29/82 ,  H01L21/268

CPC分类号： H01F41/046 ,  B81B3/0072 ,  B81B2207/015 ,  H01F17/0006 ,  H01F2017/0066 ,  H01F2017/0086 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices.

摘要翻译： 通过在晶片的钝化层的顶表面上制造大量的MEMS器件，从而通过在钝化层和钝化层之间形成应力消除层来减小在每个管芯区域上形成MEMS器件的晶片中的弓 MEMS器件。

公开(公告)号：US20110115071A1

公开(公告)日：2011-05-19

申请号：US13013563

申请日：2011-01-25

申请人： Peter Smeys ,  Peter Johnson ,  Peter Deane ,  Reda R. Razouk

发明人： Peter Smeys ,  Peter Johnson ,  Peter Deane ,  Reda R. Razouk

IPC分类号： H01L23/522 ,  H01L21/56 ,  H01L21/768

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.

摘要翻译： 描述了用于形成集成电路封装的各种装置和方法。 本发明的一个方面涉及一种集成电路封装，其中一个或多个集成电路嵌入在基片中并被一层可光成像的环氧树脂覆盖。 基板可以由各种材料制成，包括硅，石英和玻璃。 集成电路位于衬底的顶表面中的空腔内。 环氧树脂层形成在衬底的顶表面和集成电路的有源面上。 在环氧树脂层上形成互连层并与集成电路电耦合。

公开(公告)号：US20110095365A1

公开(公告)日：2011-04-28

申请号：US12589491

申请日：2009-10-23

申请人： William French ,  Peter Smeys ,  Peter J. Hopper ,  Peter Johnson

发明人： William French ,  Peter Smeys ,  Peter J. Hopper ,  Peter Johnson

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/762

CPC分类号： H01L29/7835 ,  H01L21/76898 ,  H01L29/407 ,  H01L29/66659

摘要： A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device.

摘要翻译： 一种方法包括在绝缘体上半导体结构的第一侧上形成晶体管器件。 绝缘体上半导体结构包括衬底，电介质层和衬底和电介质层之间的掩埋层。 该方法还包括通过绝缘体上半导体结构形成导电插塞。 导电插头与晶体管器件电连接。 该方法还包括在绝缘体上半导体结构的第二侧上形成场板，其中场板与导电插头电连接。 晶体管器件可以具有至少600V的击穿电压，并且场板可以沿着晶体管器件的长度的至少40％延伸。