公开(公告)号：US08300452B2

公开(公告)日：2012-10-30

申请号：US13050052

申请日：2011-03-17

申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

IPC分类号： G11C11/00

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L27/0921 ,  H01L27/1104 ,  H01L29/66181 ,  H03K3/0375

摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

摘要翻译： 数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽 电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

公开(公告)号：US20120098087A1

公开(公告)日：2012-04-26

申请号：US13342423

申请日：2012-01-03

申请人： Wagdi W. Abadeer ,  Lilian Kamal ,  Kiran V. Chatty ,  Jason E. Cummings ,  Toshiharu Furukawa ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Lilian Kamal ,  Kiran V. Chatty ,  Jason E. Cummings ,  Toshiharu Furukawa ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

IPC分类号： H01L27/12 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/265

CPC分类号： H01L29/0649 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203

摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.

摘要翻译： 用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。 在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

公开(公告)号：US08138100B2

公开(公告)日：2012-03-20

申请号：US12273908

申请日：2008-11-19

申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/00

CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上，而不是在衬底的邻接表面上，使得间隔层不完全覆盖半导体的侧壁 鳍。 可以使用侧向生长方法制造其它微电子结构。

公开(公告)号：US20110266621A1

公开(公告)日：2011-11-03

申请号：US13179635

申请日：2011-07-11

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L29/78 ,  H01L29/786

CPC分类号： H01L29/4983 ,  H01L29/4908 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78621 ,  Y10S977/742 ,  Y10S977/847

摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.

摘要翻译： 晶体管。 晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

公开(公告)号：US08043966B2

公开(公告)日：2011-10-25

申请号：US12101329

申请日：2008-04-11

申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

IPC分类号： H01L21/44

CPC分类号： H01L21/76879 ,  C25D5/10 ,  C25D5/12 ,  C25D7/123 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76802 ,  H01L22/14 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a method that both monitors patterning integrity of etched openings (i.e., ensures that lithographically patterned and etched openings are complete) and forms on-chip conductive structures (e.g., contacts, interconnects, fuses, anti-fuses, capacitors, etc.) within such openings. The method embodiments incorporate an electro-deposition process to provide both the means by which pattern integrity of etched openings can be monitored and also the metallization required for the formation of conductive structures within the openings. Specifically, during the electro-deposition process, electron flow is established by applying a current to the back side of the semiconductor wafer, thus, eliminating the need for a seed layer. Electron flow through the wafer and into the electroplating solution is then monitored and used as an indicator of electroplating in the etched openings and, thereby, as an indicator that the openings are completely etched.

摘要翻译： 公开了一种方法的实施例，两者都监控图案化蚀刻开口的完整性（即，确保光刻图案和蚀刻的开口完整），并且形成片上导电结构（例如，触点，互连，熔断器，抗熔丝，电容器等） 。）在这样的开口内。 该方法实施例包括电沉积工艺，以提供能够监测蚀刻开口的图案完整性的装置以及在开口内形成导电结构所需的金属化。 具体地，在电沉积过程中，通过向半导体晶片的背面施加电流来建立电子流动，从而消除了种子层的需要。 然后监测通过晶片并进入电镀溶液的电子流，并将其用作蚀刻开口中的电镀的指示剂，从而作为开口被完全蚀刻的指示器。

公开(公告)号：US20110204384A1

公开(公告)日：2011-08-25

申请号：US13101267

申请日：2011-05-05

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Toshiharu Furukawa ,  Xuefeng Hua

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Toshiharu Furukawa ,  Xuefeng Hua

IPC分类号： H01L27/12 ,  H01L29/12 ,  G06F17/50 ,  B82Y99/00

CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L29/1079 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78654

摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.

摘要翻译： 公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。 该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。 然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以选择性地调节凹陷侧壁的形状（即，轮廓）而不增加 凹槽 随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。 还公开了平面FET结构和平面FET的设计结构的实施例。

公开(公告)号：US07985643B2

公开(公告)日：2011-07-26

申请号：US12052855

申请日：2008-03-21

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  William Robert Tonti

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  William Robert Tonti

IPC分类号： H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114

摘要： A semiconductor structure. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.

摘要翻译： 半导体结构。 该结构包括（a）包括设置在第一和第二S / D区之间的沟道区的半导体层; （b）沟道区上的栅介质区; （c）栅极电介质区域上的栅极区域，并且通过栅极电介质区域与沟道区域电绝缘; （d）栅极区域上的保护伞区域，其中保护伞区域包括第一介电材料，并且其中栅极区域完全处于保护伞区域的阴影中; 和（e）直接在第二S / D区域上方并电连接到第二S / D区域的填充接触孔（i）和（ii）与保护伞区域的边缘对准，其中接触孔通过一个 层间介电层（ILD）层，其包括不同于第一介电材料的第二电介质材料。

公开(公告)号：US20110169129A1

公开(公告)日：2011-07-14

申请号：US13072023

申请日：2011-03-25

申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

IPC分类号： H01L23/525

CPC分类号： H01L23/5252 ,  C25D5/02 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

摘要翻译： 公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。 这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。 具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。 这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。 在电沉积期间，可以选择性地控制通过电流路径的电流。 此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

公开(公告)号：US07935621B2

公开(公告)日：2011-05-03

申请号：US12031761

申请日：2008-02-15

申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

IPC分类号： H01L21/44

CPC分类号： H01L23/5252 ,  C25D5/02 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

摘要翻译： 公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。 这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。 具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。 这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。 在电沉积期间，可以选择性地控制通过电流路径的电流。 此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

公开(公告)号：US20110095366A1

公开(公告)日：2011-04-28

申请号：US12603737

申请日：2009-10-22

申请人： Wagdi W. Abadeer ,  Lilian Kamal ,  Kiran V. Chatty ,  Jason E. Cummings ,  Toshiharu Furukawa ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Lilian Kamal ,  Kiran V. Chatty ,  Jason E. Cummings ,  Toshiharu Furukawa ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

IPC分类号： H01L29/786 ,  H01L21/762 ,  H01L29/02

CPC分类号： H01L29/0649 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203

摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.

摘要翻译： 公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。 在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。