公开(公告)号：US09935104B1

公开(公告)日：2018-04-03

申请号：US15589292

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hong Yu ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu

IPC: H01L21/84 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US09653583B1

公开(公告)日：2017-05-16

申请号：US15226165

申请日：2016-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  Hongliang Shen ,  Zhenyu Hu ,  Min-Hwa Chi

IPC: H01L21/8238 ,  H01L21/66 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes, among other things, forming a first gate structure above a fin, forming epi semiconductor material on the fin, performing at least one first etching process through a patterned sacrificial layer of material to remove at least a gate cap layer and sacrificial gate materials of the first gate structure so as to define a first isolation cavity that exposes the fin while leaving the second gate structure intact, performing at least one second etching process through the first isolation cavity to remove at least a portion of a vertical height of the fin and thereby form a first isolation trench, removing the patterned sacrificial layer of material, and forming a layer of insulating material above the epi semiconductor material and in the first isolation trench and in the first isolation cavity.

公开(公告)号：US09418899B1

公开(公告)日：2016-08-16

申请号：US14611769

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping Shen ,  Min-hwa Chi ,  Xusheng Wu ,  Weihua Tong ,  Haiting Wang

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/3215 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28568 ,  H01L21/3215 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract translation: 提供一种形成用于nFET和pFET的RMG多WF层的方法，以及所得到的器件。 实施例包括形成Si翅片; 形成nFET RMG沟槽和pFET RMG沟槽; 在nFET和pFET RMG沟槽中形成第一Ti层; 在pFET RMG沟槽中以0°注入角垂直注入第一Ti层中的N 2; 对N 2注入的第一Ti层退火以在pFET RMG沟槽中形成TiN层; 剥离第一Ti层的未反应的Ti; 在nFET和pFET RMG沟槽中形成第二Ti层; 在0°垂直放置第二Ti层中的Al或C; 退火Al或C注入的第二Ti层，分别在nFET和pFET RMG沟槽的底部形成TiAl或TiC; 并用Al或W填充nFET和pFET RMG沟槽。

公开(公告)号：US09379186B1

公开(公告)日：2016-06-28

申请号：US14610140

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qin Wang ,  Min-hwa Chi ,  Meixiong Zhao ,  Zhaoxu Shen ,  Haiting Wang ,  Lucas M. Salazar ,  Lan Yang

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/4236 ,  H01L21/823412 ,  H01L21/823456 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628

Abstract: Methods for preparing CMOS transistors having longer effective gate lengths and the resulting devices are disclosed. Embodiments include forming a dummy gate bound by spacers on opposing sides thereof, on a substrate; removing the dummy gate to form a trench between the spacers; modifying a gate channel portion of the substrate between the spacers to form inner or outer sidewalls; depositing a conformal high-k dielectric layer on the modified gate channel portion; and forming a metal gate in the trench.

Abstract translation: 公开了制备具有更长有效栅极长度的CMOS晶体管的方法和所得到的器件。 实施例包括在基板上在其相对侧上形成由间隔物结合的虚拟栅极; 去除伪栅极以在间隔物之间​​形成沟槽; 修改间隔件之间的衬底的栅极通道部分以形成内侧壁或外侧壁; 在修改的栅极沟道部分上沉积保形高k电介质层; 并在沟槽中形成金属栅极。

公开(公告)号：US20140175562A1

公开(公告)日：2014-06-26

申请号：US13727218

申请日：2012-12-26

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Haiting Wang ,  Huang Liu ,  Yong Meng Lee ,  Songkram Srivathanakul

IPC: H01L21/28 ,  H01L29/423

CPC classification number: H01L29/6653 ,  H01L21/76837 ,  H01L21/823468 ,  H01L21/823864

Abstract: A semiconductor structure in fabrication includes a NFET and a PFET. Spacers adjacent gate structures of the NFET and PFET have undesired divots that can lead to substrate damage from chemicals used in a subsequent etch. The fabrication also leaves hard masks over the gate structures with non-uniform height. The divots are filled with material resistant to the chemicals used in the etch. Excess filler is removed, and uniform height is restored. Further fabrication may then proceed.

Abstract translation: 制造中的半导体结构包括NFET和PFET。 NFET和PFET的相邻栅极结构的间隔具有不期望的凹陷，这可能导致在后续蚀刻中使用的化学品的基底损伤。 该制造也在具有不均匀高度的门结构上留下硬掩模。 这些图案填充有耐蚀刻中使用的化学品的材料。 去除多余的填料，恢复均匀的高度。 然后进一步制造。