公开(公告)号：US09461128B2

公开(公告)日：2016-10-04

申请号：US14963789

申请日：2015-12-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mark A. Zaleski ,  Andy Chih-Hung Wei ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L21/82 ,  H01L29/66 ,  H01L29/51 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L29/41758 ,  H01L21/8234 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/66727 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.

公开(公告)号：US09443931B2

公开(公告)日：2016-09-13

申请号：US14988050

申请日：2016-01-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Guillaume Bouche ,  Gabriel Padron Wells

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L21/311 ,  H01L21/308 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).

公开(公告)号：US09397004B2

公开(公告)日：2016-07-19

申请号：US14164582

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Erik Geiss ,  Scott Beasor ,  Andy Wei ,  Deniz Elizabeth Civay

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

Abstract translation: 一种用于制造finFET集成电路的方法包括提供finFET集成电路结构，其包括翅片结构，具有设置在翅片结构上并与翅片结构接触的氮化硅盖的替换金属栅极结构，包括钨材料的接触结构也布置在 并且与翅片结构接触，以及设置在替换金属栅极结构和接触结构之上的绝缘层。 所述方法还包括在所述绝缘层上形成位于所述替代栅极结构上的第一开口和在所述接触结构上的所述绝缘层中的第二开口。 形成第一和第二开口包括将FinFET集成电路结构暴露于单个极紫外光刻图案。 此外，该方法包括去除替代金属栅极结构的一部分氮化硅材料并在第一和第二开口中形成金属填充材料。

公开(公告)号：US09276064B1

公开(公告)日：2016-03-01

申请号：US14535433

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guillaume Bouche ,  Gabriel Padron Wells

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L21/311

CPC classification number: H01L29/0673 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).

Abstract translation: 提出了用于促进制造堆叠的纳米线，场效应晶体管的方法。 所述方法包括：在栅极结构上形成切割掩模间隔物，栅极结构设置在衬底结构上方的多层上方，栅极结构包括沿其侧壁的侧壁间隔物和覆盖侧壁间隔物的切割掩模间隔物; 通过使用切割掩模间隔物和栅极结构作为掩模切割多个层来限定堆叠结构，并且部分地选择性地蚀刻多个层的至少一个层以部分地掩盖掩模，其中至少一个其它层 通过选择性蚀刻，多层保持未蚀刻; 并且在栅极结构的栅极结构和多个层的上端表面上提供对准掩模间隔物，所述对准掩模间隔物有助于蚀刻多个层的另一层，以选择性地暴露部分端部表面 其他层。

公开(公告)号：US20160049490A1

公开(公告)日：2016-02-18

申请号：US14924151

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy Wei

IPC: H01L29/45 ,  H01L27/092

CPC classification number: H01L29/45 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/41725

Abstract: Integrated circuits with dual silicide contacts are provided. In an embodiment, an integrated circuit includes a semiconductor substrate including a first area and a second area. The integrated circuit includes a first source/drain region in and/or overlying the first area of the semiconductor substrate and a second source/drain region in and/or overlying the second area of the semiconductor substrate. The integrated circuit further includes a first contact over the first source/drain region and comprising a first metal silicide. The integrated circuit also includes a second contact over the second source/drain region and comprising a second metal silicide different from the first metal silicide.

Abstract translation: 提供了具有双硅化物触点的集成电路。 在一个实施例中，集成电路包括包括第一区域和第二区域的半导体衬底。 集成电路包括位于半导体衬底的第一区域内和/或覆盖半导体衬底的第一区域的第一源极/漏极区域和位于半导体衬底的第二区域内和/或覆盖半导体衬底的第二区域中的第二源极/漏极区域。 集成电路还包括在第一源极/漏极区域上的第一接触并且包括第一金属硅化物。 集成电路还包括在第二源极/漏极区域上的第二接触并且包括不同于第一金属硅化物的第二金属硅化物。

公开(公告)号：US09263325B1

公开(公告)日：2016-02-16

申请号：US14463801

申请日：2014-08-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided.

Abstract translation: 本发明的实施例提供了一种在线结构后端切割牺牲金属线的方法。 牺牲Mx + 1线形成在金属Mx线之上。 在牺牲Mx + 1线上沉积并图案化切割光刻叠层并形成切割腔。 切割腔填充有介电材料。 选择性蚀刻工艺去除牺牲Mx + 1线，保留填充切割腔的电介质。 然后通过沉积除去牺牲Mx + 1线的金属形成预切割的金属线。 因此，本发明的实施例提供预切割金属线，并且不需要金属切割。 通过避免金属切割的需要，避免与金属切割相关的风险。

公开(公告)号：US09236437B2

公开(公告)日：2016-01-12

申请号：US14184830

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mark A. Zaleski ,  Andy Chih-Hung Wei ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/41758 ,  H01L21/8234 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/66727 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.

Abstract translation: 本发明的实施例提供改进的接触形成方法。 公开了一种具有降低光刻要求的自对准接触方案。 这降低了源/漏极和栅极之间短路的风险，同时提供了改善的电路密度。 形成邻近门的腔，并且填充金属沉积在空腔中以形成接触条。 然后通过执行接触片的部分金属凹部来使用图案化掩模来形成更小的触点。

公开(公告)号：US09224842B2

公开(公告)日：2015-12-29

申请号：US14258488

申请日：2014-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

Abstract translation: 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

公开(公告)号：US20150214059A1

公开(公告)日：2015-07-30

申请号：US14166660

申请日：2014-01-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L21/28 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/2807 ,  H01L21/28158 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

Abstract: Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure.

Abstract translation: 提供了具有金属 - 绝缘体半导体（MIS）接触结构的集成电路以及用于制造具有金属 - 绝缘体 - 半导体（MIS））接触结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供由半导体材料覆盖在半导体衬底上形成的鳍结构。 该方法包括在鳍结构上沉积高k电介质材料层。 此外，该方法包括在高k电介质材料层上形成金属层，以使鳍结构具有金属 - 绝缘体半导体（MIS）接触结构。

公开(公告)号：US09093557B2

公开(公告)日：2015-07-28

申请号：US13961318

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Haiting Wang

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET having complete middle of line integration. Specifically, a hard mask layer and set of spacers are removed from the gate stacks leaving behind (among other things) a set of dummy gates. A liner layer is formed over the set of dummy gates and over a source-drain region adjacent to the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates and the source-drain region. An inter-layer dielectric (ILD) is then deposited over the set of dummy gates and over the source-drain region, and the set of dummy gates are then removed. The result is an environment in which a self-aligned contact to the source-drain region can be deposited.

Abstract translation: 通常，本发明的各方面涉及用于形成半导体器件的方法，例如具有完全中线整合的FET。 具体来说，硬掩模层和一组间隔物从栅极堆叠中移除，留下（尤其是）一组虚拟栅极。 衬套层形成在该组虚拟栅极之上并且与该组虚拟栅极相邻的源极 - 漏极区域上方。 然后将衬套层从该组虚拟栅极和源极 - 漏极区域的顶表面（或其至少一部分）移除。 然后将层间电介质（ILD）沉积在该组虚拟栅极上并在源极 - 漏极区域上方，然后去除该组虚拟栅极。 结果是可以沉积与源极 - 漏极区域的自对准接触的环境。