公开(公告)号：US09460963B2

公开(公告)日：2016-10-04

申请号：US14225529

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gabriel Padron Wells ,  Xiang Hu ,  Guillaume Bouche ,  Andre Labonte

IPC: H01L21/467 ,  H01L21/768 ,  H01L29/40 ,  H01L21/033 ,  H01L21/308 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/467 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

Abstract: Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which include gates and source/drain regions. A first etch, which may be a reactive ion etch, is used to partially recess the dielectric layer. A second etch is then used to continue the etch of the dielectric layer to form a cavity adjacent to the gate spacers. The second etch is highly selective to the spacer material, which prevents damage to the spacers during the exposure (opening) of the source/drain regions.

Abstract translation: 本发明的实施例提供了改进的接触和制造方法。 在包括栅极和源极/漏极区域的晶体管结构上形成介电层。 使用可以是反应离子蚀刻的第一蚀刻来部分地凹陷介电层。 然后使用第二蚀刻来继续蚀刻介电层以形成与栅极间隔物相邻的空腔。 第二蚀刻对间隔物材料具有高选择性，这防止了在源极/漏极区域的曝光（打开）期间损坏间隔物。

公开(公告)号：US20150279738A1

公开(公告)日：2015-10-01

申请号：US14225529

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gabriel Padron Wells ,  Xiang Hu ,  Guillaume Bouche ,  Andre Labonte

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/40 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/467 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

Abstract: Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which include gates and source/drain regions. A first etch, which may be a reactive ion etch, is used to partially recess the dielectric layer. A second etch is then used to continue the etch of the dielectric layer to form a cavity adjacent to the gate spacers. The second etch is highly selective to the spacer material, which prevents damage to the spacers during the exposure (opening) of the source/drain regions.

Abstract translation: 本发明的实施例提供了改进的接触和制造方法。 在包括栅极和源极/漏极区域的晶体管结构上形成介电层。 使用可以是反应离子蚀刻的第一蚀刻来部分地凹陷介电层。 然后使用第二蚀刻来继续蚀刻介电层以形成与栅极间隔物相邻的空腔。 第二蚀刻对间隔物材料具有高选择性，这防止了在源极/漏极区域的曝光（打开）期间损坏间隔物。

公开(公告)号：US09147680B2

公开(公告)日：2015-09-29

申请号：US13943944

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kristina Trevino ,  Yuan-Hung Lin ,  Gabriel Padron Wells ,  Chang Ho Maeng ,  Taejoon Han ,  Hoong Shing Wong

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a beveled surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.

Abstract translation: 提供了具有提高的阈值电压性能的替换金属栅极的集成电路以及用于制造这种集成电路的方法。 一种方法包括提供覆盖半导体衬底的电介质层。 电介质层具有第一和第二沟槽。 栅电介质层形成在第一和第二沟槽中。 形成覆盖栅介电层的第一阻挡层。 工作功能材料层形成在沟槽内。 功函数材料层和第一阻挡层在第一和第二沟槽中凹进。 工作功能材料层和第一阻挡层形成斜面。 栅极电介质层凹入第一和第二沟槽。 沉积导电栅电极材料，使得其填充第一和第二沟槽。 导电栅电极材料凹入第一和第二沟槽。

公开(公告)号：US20150380250A1

公开(公告)日：2015-12-31

申请号：US14318901

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Gabriel Padron Wells ,  Xiang Hu

IPC: H01L21/28 ,  H01L21/762 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/28008 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts.

Abstract translation: 本发明的实施例提供了改进的接触形成的结构和方法。 在与翅片间隔开的区域中，从栅极去除顶盖氮化物。 这有助于减少处理步骤，允许栅极和源极/漏极区域以相同的工艺步骤打开。 可以使用极紫外光刻（EUVL）来形成抗蚀剂以形成接触。

公开(公告)号：US20150311082A1

公开(公告)日：2015-10-29

申请号：US14261823

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Gabriel Padron Wells ,  Andre P. Labonte ,  Jing Wan

IPC: H01L21/28 ,  H01L29/417 ,  H01L21/283

CPC classification number: H01L29/41775 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897

Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.

Abstract translation: 提供了用于形成栅极和源极/漏极（S / D）触点的方法。 具体地说，栅极接触开口形成在一组栅极结构中的至少一个上，在半导体器件的鳍片之上形成一组S / D接触开口，并且在半导体器件上沉积金属材料以形成栅极 在门接触开口内接触一组S / D接触开口内的一组S / D接点。 在一种方法中，氮化物保留在栅极接触和至少一个S / D接触之间。 在另一种方法中，该装置包括合并门和S / D触点。 这种方法提供对分隔区域的选择性蚀刻，其中氧化物将被进一步选择性地去除氮化物以产生空穴以金属化并产生与S / D的接触，而接触区域之间的隔离区域被氮化物包围并且在氧化物蚀刻期间不被去除 。

公开(公告)号：US20150303295A1

公开(公告)日：2015-10-22

申请号：US14258279

申请日：2014-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Xiang Hu ,  Jinping Liu ,  Gabriel Padron Wells ,  Andy Chih-Hung Wei ,  Guillaume Bouche ,  Cuiqin Xu

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/51 ,  H01L29/66795 ,  H01L2029/7858

Abstract: Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings.

Abstract translation: 提供了在半导体器件（例如，FinFET器件）中形成一组接触开口的方法。 具体地，半导体器件包括形成在衬底中的一组翅片，形成在衬底上的栅极结构（例如，替换金属栅极（RMG））以及与栅极结构相邻的一组接触开口，该组接触 具有顶部和底部的开口，其中沿着栅极结构的长度的底部的宽度大于顶部的宽度。 半导体器件还包括形成在该组接触开口内的一组金属触头。

公开(公告)号：US09443931B2

公开(公告)日：2016-09-13

申请号：US14988050

申请日：2016-01-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Guillaume Bouche ,  Gabriel Padron Wells

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L21/311 ,  H01L21/308 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).

公开(公告)号：US09276064B1

公开(公告)日：2016-03-01

申请号：US14535433

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guillaume Bouche ,  Gabriel Padron Wells

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L21/311

CPC classification number: H01L29/0673 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).

Abstract translation: 提出了用于促进制造堆叠的纳米线，场效应晶体管的方法。 所述方法包括：在栅极结构上形成切割掩模间隔物，栅极结构设置在衬底结构上方的多层上方，栅极结构包括沿其侧壁的侧壁间隔物和覆盖侧壁间隔物的切割掩模间隔物; 通过使用切割掩模间隔物和栅极结构作为掩模切割多个层来限定堆叠结构，并且部分地选择性地蚀刻多个层的至少一个层以部分地掩盖掩模，其中至少一个其它层 通过选择性蚀刻，多层保持未蚀刻; 并且在栅极结构的栅极结构和多个层的上端表面上提供对准掩模间隔物，所述对准掩模间隔物有助于蚀刻多个层的另一层，以选择性地暴露部分端部表面 其他层。

公开(公告)号：US20150021694A1

公开(公告)日：2015-01-22

申请号：US13943944

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kristina Trevino ,  Yuan-Hung Lin ,  Gabriel Padron Wells ,  Chang Ho Maeng ,  Taejoon Han ,  Hoong Shing Wong

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a chamfered surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.

Abstract translation: 提供了具有提高的阈值电压性能的替换金属栅极的集成电路以及用于制造这种集成电路的方法。 一种方法包括提供覆盖半导体衬底的电介质层。 电介质层具有第一和第二沟槽。 栅电介质层形成在第一和第二沟槽中。 形成覆盖栅介电层的第一阻挡层。 工作功能材料层形成在沟槽内。 功函数材料层和第一阻挡层在第一和第二沟槽中凹进。 工作功能材料层和第一阻挡层形成倒角表面。 栅极电介质层凹入第一和第二沟槽。 沉积导电栅电极材料，使得其填充第一和第二沟槽。 导电栅电极材料凹入第一和第二沟槽。

公开(公告)号：US09640625B2

公开(公告)日：2017-05-02

申请号：US14261823

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Gabriel Padron Wells ,  Andre P. Labonte ,  Jing Wan

IPC: H01L29/76 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L29/41775 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897

Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.