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101.发明授权Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming 失效需要双极性编程的双极型二极管三维存储器的解码方案公开(公告)号：US08755213B2
公开(公告)日：2014-06-17
申请号：US13407848
申请日：2012-02-29
CPC分类号： G11C13/0069 , G11C5/025 , G11C8/10 , G11C8/14 , G11C11/16 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0023 , G11C2013/0071 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/77
摘要： A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.
摘要翻译： 一种用于操作包括双向存取二极管的双极存储单元阵列的系统和方法。 该系统包括列电压。 列电压开关包括列电压和电耦合到双向存取二极管的输出。 列电压包括至少一个写一列电压和至少一个写零列电压。 该系统还包括行电压开关。 行电压开关包括行电压和电耦合到双向存取二极管的输出。 行电压包括至少一个写入一行电压和至少一个写入零行电压。 该系统还包括分别与列电压开关和行电压开关的选择线电耦合的列解码器和行解码器。 该系统包括电耦合到行和列开关的选择线的写入驱动器。
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公开(公告)号：US08728859B2
公开(公告)日：2014-05-20
申请号：US12855079
申请日：2010-08-12
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683 , H01L45/1691
摘要： An example embodiment disclosed is a method for fabricating a phase change memory cell. The method includes forming a non-sublithographic via within an insulating substrate. The insulating substrate is embedded on the same layer as a first metalization layer (Metal 1) of a semiconductor wafer, and includes a bottom and a sidewall. A sublithographic aperture is formed through the bottom of the non-sublithographic via and extends to a buried conductive material. The sublithographic aperture is filled with a conductive non-phase change material. Furthermore, phase change material is deposited within the non-sublithographic via.
摘要翻译： 所公开的示例性实施例是用于制造相变存储单元的方法。 该方法包括在绝缘衬底内形成非亚光刻通孔。 绝缘基板被嵌入与半导体晶片的第一金属化层（金属1）相同的层上，并且包括底部和侧壁。 通过非亚光刻通孔的底部形成亚光刻孔，并延伸到掩埋的导电材料。 亚光刻孔填充有导电非相变材料。 此外，相变材料沉积在非亚光刻通孔内。
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公开(公告)号：US08686391B2
公开(公告)日：2014-04-01
申请号：US13612552
申请日：2012-09-12
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.
摘要翻译： 提供一种制造电极的方法，其包括在电介质层的导电结构的顶部设置第一相变材料的柱; 或倒置结构; 在电介质层的上方形成绝缘材料，并邻近所述柱，其中所述第一绝缘材料的上表面与所述柱的上表面共面; 将所述柱的上表面凹陷在所述绝缘材料的上表面下方以提供凹腔; 以及在所述凹腔和所述绝缘材料的上表面之上形成第二相变材料，其中所述第二相变材料具有比所述第一相变材料更大的相电阻率。
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公开(公告)号：US08638598B1
公开(公告)日：2014-01-28
申请号：US13551574
申请日：2012-10-01
申请人： Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5678
摘要： An example embodiment is a method for determining a binary value of a memory cell represented by an electrical resistance level of the memory cell. The method includes iteratively charging shunt capacitors having different capacitances until a selected shunt capacitor causes the voltage to decay through the memory cell to a reference voltage within a predetermined time range. A binary value of the most significant bits of the memory cell is determined based on the selected shunt capacitor. The selected shunt capacitor is then charged to a second voltage and the binary value of the least significant bits of the memory cell is determined based on a decay of the second voltage at the selected shunt capacitor through the memory cell.
摘要翻译： 示例性实施例是用于确定由存储器单元的电阻级别表示的存储器单元的二进制值的方法。 该方法包括迭代地对具有不同电容的并联电容器进行充电，直到所选择的并联电容器使得电压在预定时间范围内通过存储器单元衰减到参考电压。 基于所选择的并联电容器来确定存储器单元的最高有效位的二进制值。 所选择的并联电容器然后被充电到第二电压，并且基于通过存储器单元在所选择的并联电容器处的第二电压的衰减来确定存储器单元的最低有效位的二进制值。
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公开(公告)号：US20140026008A1
公开(公告)日：2014-01-23
申请号：US13551728
申请日：2012-07-18
申请人： Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Chung H. Lam , Jing Li , Robert K. Montoye
CPC分类号： G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C15/046 , G11C29/32 , G11C29/44
摘要： A system for programming a phase change material-content addressable memory (PCM-CAM). The system includes a receiving unit for receiving a word to be written in the PCM-CAM. The word includes low bits represented by a low resistance state in the PCM-CAM and high bits represented by a high resistance state in the PCM-CAM. The system includes a writing unit configured to repeatedly write the low bits in memory cells of the PCM-CAM until the resistance of the memory cells are below a threshold value, and to write high bits in memory cells of the PCM-CAM only once.
摘要翻译： 用于编程相变材料内容可寻址存储器（PCM-CAM）的系统。 该系统包括用于接收要写入PCM-CAM中的单词的接收单元。 该字包括由PCM-CAM中的低电阻状态表示的低位和由PCM-CAM中的高电阻状态表示的高位。 该系统包括：写入单元，被配置为重复写入PCM-CAM的存储单元中的低位，直到存储器单元的电阻低于阈值，并且仅在PCM-CAM的存储器单元中写入高位一次。
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106.发明申请SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR 有权具有环绕门控存取晶体管的存储器单元阵列的自对准过程公开(公告)号：US20140021533A1
公开(公告)日：2014-01-23
申请号：US13587694
申请日：2012-08-16
申请人： Matthew J. BrightSky , Chung H. Lam , Gen P. Lauer
发明人： Matthew J. BrightSky , Chung H. Lam , Gen P. Lauer
IPC分类号： H01L27/088
CPC分类号： H01L27/101 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A memory array including a plurality of memory cells. In one embodiment, each memory cell is coupled to an electrically conductive gate material. A word line is coupled to the gate material at a contact interface level. A pair of pillars is comprised of an insulating material that extends below the contact interface level. Also, a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, forming a pair of pillars comprised of an insulating material and depositing a gate contact between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level and the insulating material extends below the contact interface level.
摘要翻译： 一种包括多个存储单元的存储器阵列。 在一个实施例中，每个存储器单元耦合到导电栅极材料。 字线在接触界面层与栅极材料耦合。 一对支柱由在接触界面下方延伸的绝缘材料构成。 而且，一种防止栅极接触与衬底上的多个存储单元的源极接触电连接的方法。 该方法包括沉积和蚀刻栅极材料以部分地填充柱之间的空间并且形成用于存储器单元的字线，形成由绝缘材料构成的一对柱，并在该对柱之间沉积栅极接触，使得 栅极接触件在接触界面处将栅极材料电耦合，绝缘材料延伸到接触界面的下方。
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公开(公告)号：US08623734B2
公开(公告)日：2014-01-07
申请号：US13150559
申请日：2011-06-01
IPC分类号： H01L21/20
CPC分类号： H01L45/06 , G11C13/0004 , H01L21/31144 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/1683
摘要： An example embodiment is a method for filling a via hole with phase change material. The method steps include forming a bottom electrode in a substrate, depositing a dielectric layer above the bottom electrode, and forming a via hole within the dielectric layer down to a top surface of the bottom electrode. The substrate is heated to a reaction temperature and a first phase change material precursor is deposited within the via hole. The first precursor is configured to decompose on the top surface of the bottom electrode and chemisorb on a top surface of the dielectric layer at the reaction temperature. A second precursor is deposited within the via hole after the first precursor at least partially decomposes on the top surface of the bottom electrode.
摘要翻译： 一个示例性实施例是用相变材料填充通孔的方法。 所述方法步骤包括在衬底中形成底部电极，在所述底部电极上沉积介电层，以及在所述电介质层内形成通孔至所述底部电极的顶表面。 将基板加热至反应温度，并且在通孔内沉积第一相变材料前体。 第一前体被配置为在反应温度下在底部电极的顶表面上和在电介质层的顶表面上分解化学吸附物。 在第一前体之后，第二前体沉积在通孔内，在底部电极的顶表面上至少部分分解。
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公开(公告)号：US08614911B2
公开(公告)日：2013-12-24
申请号：US13335155
申请日：2011-12-22
申请人： Chung H. Lam , Jing Li
发明人： Chung H. Lam , Jing Li
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C13/0004 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0092
摘要： A drive circuit and method for parallel programming a plurality of phase change memory (PCM) cells includes a first signal generator device for generating a slow ramping signal; an adiabatic computing element receives the slow ramping signal and responsively generates an output slow ramping signal in adiabatic fashion, the output slow ramping signal applied to the single wordline conductor associated with each PCM cell of the plurality of cells being programmed in a time interval. Each PCM cell of the plurality being programmed is connected to a respective bitline conductor. A second signal generator generates, during the time interval, one or more bitline signals for input to a respective bitline conductor of a respective PCM cell. A state of the applied slow ramping output signal and the one or more bitline signals during the time interval governs a programmed state of the PCM cell.
摘要翻译： 用于并行编程多个相变存储器（PCM）单元的驱动电路和方法包括：用于产生缓慢斜坡信号的第一信号发生器装置; 绝热计算元件接收缓慢斜坡信号并且以绝热方式响应地产生输出缓慢斜坡信号，施加到与多个单元中的每个PCM单元相关联的单个字线导体的输出缓慢斜坡信号在时间间隔内被编程。 被编程的多个PCM单元连接到相应的位线导体。 第二信号发生器在时间间隔期间产生用于输入到相应PCM单元的相应位线导体的一个或多个位线信号。 在时间间隔期间所施加的缓慢斜坡输出信号和一个或多个位线信号的状态控制PCM单元的编程状态。
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109.发明授权Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor 有权自对准工艺制造具有周围栅极存取晶体管的存储单元阵列公开(公告)号：US08592250B2
公开(公告)日：2013-11-26
申请号：US13364311
申请日：2012-02-01
申请人： Matthew J. BrightSky , Chung H. Lam , Gen P. Lauer
发明人： Matthew J. BrightSky , Chung H. Lam , Gen P. Lauer
IPC分类号： H01L29/02
CPC分类号： H01L45/06 , H01L27/2454 , H01L45/143 , H01L45/144
摘要： A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars made of an insulating material over the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.
摘要翻译： 一种包括多个存储单元的存储器阵列。 每个字线电耦合到一组存储器单元，栅极接触和平行于字线定位的一对电介质柱。 绝缘柱放置在栅极接触的两侧。 也是防止栅极接触与衬底上的多个存储器单元的源极接触电连接的方法。 该方法包括在衬底上形成由绝缘材料制成的一对支柱，在支柱之间和之上沉积导电栅极材料，蚀刻栅极材料，使得其部分地填充一对柱之间的空间并形成 用于存储单元的字线，以及在介电柱之间沉积栅极接触，使得栅极接触与栅极材料电接触。
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公开(公告)号：US08558210B2
公开(公告)日：2013-10-15
申请号：US13449378
申请日：2012-04-18
申请人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
发明人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/0623 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.
摘要翻译： 具有与整个存储单元结合形成的双极结型晶体管（BJT）存取装置的电阻性非易失性存储单元。 存储单元包括用作集电极的基板，用作基极的半导体基极层和用作发射极的半导体发射极层。 此外，金属插头和相变存储元件形成在BJT存取装置的上方，而发射极，金属插塞和相变存储元件包含在绝缘区域内。 在本发明的一个实施例中，形成间隔层，并且发射极层包含在保护间隔层内。 间隔层包含在绝缘区域内。
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