摘要:
A method for forming a self-aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of the substrate; and allowing at least a portion of the masking material to preferential develop in a fashion that is replicates the existing pattern of the substrate. The existing pattern may be comprised of a first set of regions of the substrate having a first reflectivity and a second set of regions of the substrate having a second reflectivity different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. Structures made in accordance with the method.
摘要:
Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO2) as a carrier or chlorodiflouromethane itself in supercritical form. The invention also includes a method of forming a nano-structure including exposing a polymeric film to a polar supercritical solvent to develop at least a portion of the polymeric film. The invention also includes a method of removing a poly(methyl methacrylate-b-styrene) (PMMA-b-S) based resist using a polar supercritical solvent.
摘要翻译:公开了使用极性超临界溶剂显影或除去嵌段共聚物膜的选择区域以溶解选择部分的方法。 在一个实施方案中,极性超临界溶剂包括氯二氟甲烷,其可以使用超临界二氧化碳(CO 2 CO 2)作为载体或氯二氟乙烷本身以超临界形式暴露于嵌段共聚物膜。 本发明还包括形成纳米结构的方法,包括将聚合物膜暴露于极性超临界溶剂以形成至少一部分聚合物膜。 本发明还包括使用极性超临界溶剂除去聚(甲基丙烯酸甲酯-b-苯乙烯)(PMMA-b-S)基抗蚀剂的方法。
摘要:
A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of inter connect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
摘要:
A method (and apparatus) of imprint lithography, includes imprinting, via a patterned mask, a pattern into a resist layer on a substrate, and overlaying a cladding layer over the imprinted resist layer. A portion of the cladding layer is used as a hard mask for a subsequent processing.
摘要:
Methods of multiple exposure in the fields of deep ultraviolet photolithography, next generation lithography, and semiconductor fabrication comprise a spin-castable methodology for enabling multiple patterning by completing a standard lithography process for the first exposure, followed by spin casting an etch selective overcoat layer, applying a second photoresist, and subsequent lithography. Utilizing the etch selectivity of each layer, provides a cost-effective, high resolution patterning technique. The invention comprises a number of double or multiple patterning techniques, some aimed at achieving resolution benefits, as well as others that achieve cost savings, or both resolution and cost savings. These techniques include, but are not limited to, pitch splitting techniques, pattern decomposition techniques, and dual damascene structures.
摘要:
A method (and apparatus) for nano lithography, includes applying a pneumatic pressure to at least one of a surface of a semi-rigid mask or template and a portion of a surface of a resist-coated workpiece, and, by the applying of the pneumatic pressure, transferring a pattern from the mask to the workpiece.
摘要:
A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.
摘要:
Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
摘要:
A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要:
A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.