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    Methods of Forming Integrated Assemblies Having Conductive Material Along Sidewall Surfaces of Semiconductor Pillars
    102.
    发明申请
    Methods of Forming Integrated Assemblies Having Conductive Material Along Sidewall Surfaces of Semiconductor Pillars 审中-公开

    公开(公告)号：US20200111797A1

    公开(公告)日：2020-04-09

    申请号：US16150412

    申请日：2018-10-03

    Applicant: Micron Technology, Inc.

    Inventor： Hong Li ,  Ramaswamy Ishwar Venkatanarayanan ,  Sanh D. Tang ,  Erica L. Poelstra

    IPC: H01L27/108 ,  G11C11/402 ,  H01L23/538 ,  H01L23/49

    Abstract: Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.

    Memory arrays
    103.
    发明授权
    Memory arrays 有权

    公开(公告)号：US10607995B2

    公开(公告)日：2020-03-31

    申请号：US15973697

    申请日：2018-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Martin C. Roberts ,  Sanh D. Tang ,  Fred D. Fishburn

    IPC: H01L27/108 ,  H01L29/08 ,  H01L29/10 ,  H01L49/02 ,  H01L23/528 ,  H01L29/423 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11514 ,  H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/06

    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed.

    Method of forming an array of capacitors, a method of forming DRAM circuitry, and a method of forming an elevationally-elongated conductive structure of integrated circuitry
    104.
    发明授权
    Method of forming an array of capacitors, a method of forming DRAM circuitry, and a method of forming an elevationally-elongated conductive structure of integrated circuitry 有权

    公开(公告)号：US10475796B1

    公开(公告)日：2019-11-12

    申请号：US16021709

    申请日：2018-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Kuo-Chen Wang ,  Sanh D. Tang

    IPC: H01L27/088 ,  H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532 ,  H01L29/423 ,  H01L29/08

    Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias individually having an upper horizontal perimeter. The conductive vias individually have an upper horizontal perimeter. Masking material is formed directly above the conductive vias. An opening is formed in the masking material directly above individual of the upper horizontal perimeters of individual of the conductive vias. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below. Conductive material is formed in the individual masking-material openings against sidewalls of the individual masking-material openings and directly against the conductive via directly there-below. An upper horizontal perimeter of the conductive material in the individual masking-material openings extends outwardly beyond the upper horizontal perimeter of the conductive via directly there-below.

    Memory Arrays Comprising Memory Cells
    105.
    发明申请
    Memory Arrays Comprising Memory Cells 审中-公开

    公开(公告)号：US20190103406A1

    公开(公告)日：2019-04-04

    申请号：US16192462

    申请日：2018-11-15

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Martin C. Roberts ,  Gurtej S. Sandhu

    IPC: H01L27/108 ,  H01L29/786

    Abstract: Some embodiments include a memory array having vertically-stacked memory cells. Each of the memory cells includes a transistor coupled with a charge-storage device, and each of the transistors has channel material with a bandgap greater than 2 electron-volts. Some embodiments include a memory array having digit lines extending along a vertical direction and wordlines extending along a horizontal direction. The memory array includes memory cells, with each of the memory cells being uniquely addressed by combination of one of the digit lines and one of the wordlines. Each of the memory cells includes a transistor which has GaP channel material. Each of the transistors has first and second source/drain regions spaced from one another by the GaP channel material. The first source/drain regions are coupled with the digit lines, and each of the memory cells includes a capacitor coupled with the second source/drain region of the associated transistor. Other embodiments are disclosed.

    Structure of integrated circuitry and a method of forming a conductive via
    110.
    发明授权
    Structure of integrated circuitry and a method of forming a conductive via 有权

    公开(公告)号：US10128183B1

    公开(公告)日：2018-11-13

    申请号：US15926505

    申请日：2018-03-20

    Applicant: Micron Technology, Inc.

    Inventor： Sourabh Dhir ,  Andrew L. Li ,  Sanh D. Tang ,  Naoyoshi Kobayashi ,  Katsumi Koge

    IPC: H01L23/522 ,  H01L21/768

    Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

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