公开(公告)号：US10223204B2

公开(公告)日：2019-03-05

申请号：US13994609

申请日：2011-12-22

申请人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

发明人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/10

摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US09529592B2

公开(公告)日：2016-12-27

申请号：US12005575

申请日：2007-12-27

申请人： Doron Orenstien ,  Zeev Sperber ,  Bob Valentine ,  Benny Eitan

发明人： Doron Orenstien ,  Zeev Sperber ,  Bob Valentine ,  Benny Eitan

IPC分类号： G06F9/312 ,  G06F9/30 ,  G06F9/38 ,  G06F15/80

CPC分类号： G06F9/30043 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/3842 ,  G06F9/3861 ,  G06F15/8061

摘要： In one embodiment, logic is provided to receive and execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction, such that only portions of the plurality of packed data elements are transferred to the destination location. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，提供逻辑以接收和执行掩码移动指令，以将包含多个打包数据元素的向量数据元素从源位置传送到目的地位置，经受指令的掩码信息，使得只有部分 多个打包数据元素被传送到目的地位置。 描述和要求保护其他实施例。

公开(公告)号：US20160179545A1

公开(公告)日：2016-06-23

申请号：US14581268

申请日：2014-12-23

申请人： Kamil Garifullin ,  Stanislav Shwartsman ,  Lihu Rappoport ,  Zeev Sperber ,  Pavel I. Kryukov ,  Andrey Kluchnikov ,  Igor Yanover ,  George Leifman ,  Alex Gerber ,  Jared W. Stark

发明人： Kamil Garifullin ,  Stanislav Shwartsman ,  Lihu Rappoport ,  Zeev Sperber ,  Pavel I. Kryukov ,  Andrey Kluchnikov ,  Igor Yanover ,  George Leifman ,  Alex Gerber ,  Jared W. Stark

IPC分类号： G06F9/38

CPC分类号： G06F9/384 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30116 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3891

摘要： A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.

摘要翻译： 处理器包括核心，存储器子系统，预测器模块和存储器重命名模块。 预测器模块可以包括用于识别存储指令和加载指令之间的依赖性的第一逻辑，以及基于所识别的依赖关系将存储器重命名（MRN）寄存器分配给存储指令和加载指令的第二逻辑。 此外，存储器重命名模块可以包括第三逻辑，用于基于所分配的MRN寄存器将与存储指令相关联的第一逻辑寄存器中的信息直接复制到与加载指令相关联的第二逻辑寄存器。

公开(公告)号：US09229524B2

公开(公告)日：2016-01-05

申请号：US13534601

申请日：2012-06-27

申请人： Nadav Bonen ,  Ron Gabor ,  Zeev Sperber ,  Vjekoslav Svilan ,  David N. Mackintosh ,  Jose A. Baiocchi Paredes ,  Naveen Kumar ,  Shantanu Gupta

发明人： Nadav Bonen ,  Ron Gabor ,  Zeev Sperber ,  Vjekoslav Svilan ,  David N. Mackintosh ,  Jose A. Baiocchi Paredes ,  Naveen Kumar ,  Shantanu Gupta

IPC分类号： G06F1/32 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F1/3243 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/3869 ,  G06F9/3885 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/152 ,  Y02D10/171

摘要： In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括执行单元，用于执行第一类型的指令，耦合到执行单元的本地电源门电路，以在第二执行单元执行第二类型的指令时对所述执行单元进行电源门控，以及 控制器，其耦合到所述本地电源门电路，以使得当指令流不包括所述第一类型的指令时，所述控制器对所述执行单元进行供电。 描述和要求保护其他实施例。

公开(公告)号：US08606841B2

公开(公告)日：2013-12-10

申请号：US13656634

申请日：2012-10-19

申请人： Rajiv Kapoor ,  Ronen Zohar ,  Mark J. Buxton ,  Zeev Sperber ,  Koby Gottlieb

发明人： Rajiv Kapoor ,  Ronen Zohar ,  Mark J. Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC分类号： G06F7/50

CPC分类号： G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

摘要： A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

公开(公告)号：US20130166883A1

公开(公告)日：2013-06-27

申请号：US13763596

申请日：2013-02-08

申请人： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

发明人： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC分类号： G06F9/30

CPC分类号： G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

摘要： A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

公开(公告)号：US20110208918A1

公开(公告)日：2011-08-25

申请号：US12978513

申请日：2010-12-24

申请人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

发明人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/30032 ,  G06F9/3824 ,  G06F9/384 ,  Y02D10/13

摘要： Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

摘要翻译： 描述与硬件移动消除和/或下一页预取相关的方法和装置。 在一些实施例中，逻辑可以基于存储的数据提供硬件移动消除。 在一个实施例中，公开了下一页预取器。 还描述和要求保护其他实施例。

公开(公告)号：US20090328057A1

公开(公告)日：2009-12-31

申请号：US12164666

申请日：2008-06-30

申请人： Sagi LAHAV ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

发明人： Sagi LAHAV ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

IPC分类号： G06F9/445

CPC分类号： G06F9/3838 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3859

摘要： A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.

摘要翻译： 设备和方法可以获取用于执行的指令或微操作。 可以指示该指令是否取决于对应于一组先前获取的指令的任何源值。 可以存储对应于第一指令所依赖的每个源值的值。 可以针对指令的每个源的指示，源是否依赖于先前加载的值或源，其中指示可以包括存储对应于指示的值。 可以在与指令相关联的存储值表示满足依赖性之后执行指令。

公开(公告)号：US07389406B2

公开(公告)日：2008-06-17

申请号：US10950690

申请日：2004-09-28

申请人： Zeev Sperber ,  Guillermo Savransky ,  Sagi Lahav

发明人： Zeev Sperber ,  Guillermo Savransky ,  Sagi Lahav

IPC分类号： G06F9/30

CPC分类号： G06F9/3857 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3867 ,  G06F9/3887

摘要： A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of through the splittable execution unit to generate a second partial execution result of the micro-operation. The first partial execution result and second partial execution result are concatenated into a full execution result.

摘要翻译： 可拆分执行单元的部分执行单元对微操作的一个或多个参数的一部分执行操作，以产生微操作的第一部分执行结果。 其中一个参数的补充部分通过旁路执行单元而不是通过可分割执行单元传递，以生成微操作的第二部分执行结果。 第一部分执行结果和第二部分执行结果被连接成一个完整的执行结果。

公开(公告)号：US20070005940A1

公开(公告)日：2007-01-04

申请号：US11170076

申请日：2005-06-30

申请人： Zeev Sperber ,  Guillermo Savransky ,  Sagi Lahav ,  Thierry Pons ,  Stephan Jourdan

发明人： Zeev Sperber ,  Guillermo Savransky ,  Sagi Lahav ,  Thierry Pons ,  Stephan Jourdan

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3832

摘要： Embodiments of the present invention provide an apparatus, system, and method of routing a source operand. Some demonstrative embodiments my include replacing a source operand of a micro operation to be executed by an execution unit with a value type representing a source value, e.g., if the source operand corresponds to the source value. Other embodiments are described and claimed.

摘要翻译： 本发明的实施例提供了一种用于路由源操作数的装置，系统和方法。 一些说明性实施例，我的包括用代表源值的值类型替换由执行单元执行的微操作的源操作数，例如，如果源操作数对应于源值。 描述和要求保护其他实施例。