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107 条记录 (耗时 0.023 秒)

    Advance metallization process
    105.
    发明授权
    Advance metallization process 有权
    推进金属化过程

    公开(公告)号：US06281109B1

    公开(公告)日：2001-08-28

    申请号：US09571074

    申请日：2000-05-15

    申请人： Manny Ma ,  Trung Doan ,  Jeff Zhiqiang Wu

    发明人： Manny Ma ,  Trung Doan ,  Jeff Zhiqiang Wu

    IPC分类号： H01L214763

    CPC分类号： H01L21/76838 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.

    摘要翻译： 本发明的示例性实施方案包括一种用于形成在半导体器件中制造导电线的方法，该方法包括以下步骤：在支撑材料上形成具有基本上垂直的侧壁的图案化导电线的第一层; 围绕所述基本上垂直的侧壁形成绝缘隔离物; 将沟槽形成到与绝缘间隔件对准的支撑材料中; 并且形成图案化导电线的第二层，使得每条线至少部分地嵌入相应的沟槽内。 优选地，由双金属工艺形成的导线凹入到具有基本上平坦的表面的支撑材料中。

    Etch process for aligning a capacitor structure and an adjacent contact corridor
    106.
    发明授权
    Etch process for aligning a capacitor structure and an adjacent contact corridor 有权
    用于对齐电容器结构和相邻触点走廊的蚀刻工艺

    公开(公告)号：US06274423B1

    公开(公告)日：2001-08-14

    申请号：US09236761

    申请日：1999-01-25

    申请人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

    发明人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

    IPC分类号： H01L218242

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.

    摘要翻译： 用于增加动态随机存取存储器中电容器组件与相邻触点走廊之间的对准公差的蚀刻工艺。 该蚀刻工艺在形成于半导体衬底上的电容器结构中实施。电容器结构包括第一导体，第一导体上的电介质层和介电层上的第二导体。 第二导体具有横向邻近并远离第一导体延伸的水平区域。 蚀刻工艺包括以下步骤：（a）在第二导体上形成图案化光致抗蚀剂层，光刻胶被图案化以在第二导体的水平区域的一个源/ 漏极区域; （b）使用光致抗蚀剂作为蚀刻掩模，各向异性地蚀刻掉第二导体的水平区域的暴露部分; 和（c）再次使用光致抗蚀剂作为蚀刻掩模，各向同性地蚀刻掉第二导体的水平区域的基本上所有其余部分，从而扩大可用于定位接触走廊的面积。 或者，使用单个各向同性蚀刻去除第二导体的水平区域。

    Uniform dielectric layer and method to form same
    107.
    发明授权
    Uniform dielectric layer and method to form same 有权

    公开(公告)号：US06235571B1

    公开(公告)日：2001-05-22

    申请号：US09283116

    申请日：1999-03-31

    申请人： Trung Doan

    发明人： Trung Doan

    IPC分类号： H01L218242

    CPC分类号： H01L28/40 ,  H01L21/3185 ,  H01L21/3211 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/91

    摘要： An exemplary embodiment of the present invention discloses a method for forming a forming a storage capacitor having a uniform dielectric film, by a the steps of: forming a bottom electrode of the storage capacitor and an insulation material about the bottom electrode, the bottom electrode comprises a nitridation receptive material and the insulation material comprises a nitridation resistive material; depositing a layer of non-doped silicon to a thickness of 20 Å or less over the bottom electrode and the insulation material; converting the silicon layer to a silicon nitride compound; depositing a silicon nitride of uniform thickness directly on the silicon nitride compound while using the silicon nitride compound as a nitride-nucleation enhancing surface; exposing the silicon nitride compound and the silicon nitride layer to an oxidation ambient to form a storage capacitor dielectric film; and then forming a top electrode of the storage capacitor over the storage capacitor dielectric film.