公开(公告)号：US20090179253A1

公开(公告)日：2009-07-16

申请号：US11811958

申请日：2007-06-13

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L21/0214 ,  C23C16/0272 ,  C23C16/308 ,  G11C16/0466 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/3145 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/518 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.

Abstract translation: 提供了包括具有多层电荷存储层的氧化物 - 氧化物 - 氧化物（ONO）结构的半导体器件及其形成方法。 通常，该方法包括：（i）形成ONO结构的第一氧化物层; （ii）在所述第一氧化物层的表面上形成包含氮化物的多层电荷存储层; 和（iii）在多层电荷存储层的表面上形成ONO结构的第二氧化物层。 优选地，电荷存储层包括至少两个氧氮，氮和/或硅具有不同化学计量组成的氮氧化硅层。 更优选地，ONO结构是氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）结构的一部分，并且半导体器件是SONOS存储晶体管。 还公开了其他实施例。

公开(公告)号：US20080296664A1

公开(公告)日：2008-12-04

申请号：US12185751

申请日：2008-08-04

Applicant: Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

公开(公告)号：US20080293255A1

公开(公告)日：2008-11-27

申请号：US12124855

申请日：2008-05-21

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L21/31

CPC classification number: H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed Thereon. A portion of the charge-trapping layer is then oxidized to form a blocking Dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.

Abstract translation: 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括提供其上设置有电荷捕获层的衬底。 然后通过将电荷捕获层暴露于自由基氧化过程，电荷俘获层的一部分被氧化以形成电荷俘获层上方的阻挡介电层。

公开(公告)号：US20080293254A1

公开(公告)日：2008-11-27

申请号：US11904513

申请日：2007-09-26

Applicant: Krishnaswamy Ramkumar ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Sagy Levy

IPC: H01L21/314

CPC classification number: H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833 ,  Y10S438/954

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

Abstract translation: 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括首先在单晶片簇工具的第一处理室中的衬底上形成隧道电介质层。 然后在单晶片簇工具的第二处理室中的隧道介电层上形成电荷捕获层。 然后在单晶片簇工具的第二或第三处理室中的电荷俘获层上形成顶部电介质层。

公开(公告)号：US20080293207A1

公开(公告)日：2008-11-27

申请号：US12125864

申请日：2008-05-22

Applicant: William W.C. Koutny, JR. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

Inventor： William W.C. Koutny, JR. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract translation: 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

公开(公告)号：US07256083B1

公开(公告)日：2007-08-14

申请号：US10185646

申请日：2002-06-28

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L21/8238

CPC classification number: H01L21/28247 ,  H01L21/28061 ,  H01L29/4941

Abstract: A method of making a semiconductor structure includes depositing a nitride layer, on a metallic layer, by PECVD. The metallic layer is on a gate layer containing silicon, and the gate layer is on a semiconductor substrate.

Abstract translation: 制造半导体结构的方法包括通过PECVD在金属层上沉积氮化物层。 金属层位于含硅的栅极层上，栅极层位于半导体衬底上。

公开(公告)号：US07026235B1

公开(公告)日：2006-04-11

申请号：US10072164

申请日：2002-02-07

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, an interconnect line on one level of an integrated circuit is electrically coupled to another interconnect line on another level. The two layers of interconnects may be coupled together using a via. To reduce capacitance between the interconnect lines, an air core is formed between them. The air core may be formed by using a chemistry that includes a noble gas fluoride to etch a sacrificial layer between the interconnect layers.

Abstract translation: 在一个实施例中，集成电路的一个电平上的互连线电连接到另一个电平上的另一个互连线。 两层互连可以使用通孔耦合在一起。 为了减小互连线之间的电容，在它们之间形成空芯。 空芯可以通过使用包含惰性气体氟化物的化学物质来形成，以蚀刻互连层之间的牺牲层。

公开(公告)号：US06969684B1

公开(公告)日：2005-11-29

申请号：US09846119

申请日：2001-04-30

Applicant: Yitzhak Gilboa ,  William W. C. Koutny, Jr. ,  Steven Hedayati ,  Krishnaswamy Ramkumar

Inventor： Yitzhak Gilboa ,  William W. C. Koutny, Jr. ,  Steven Hedayati ,  Krishnaswamy Ramkumar

IPC: H01L21/302 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/31055

Abstract: A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.

Abstract translation: 提供了一种从抛光过程中消除抛光停止层的方法。 特别地，提供了一种方法，其可以包括抛光半导体形貌的上层以形成在下层之上的高度上的上表面，其中上表面不包括抛光停止材料。 优选地，通过抛光形成的形貌的上表面被充分地间隔在下面的层上，以避免抛光下面的层。 可以同时蚀刻整个上表面以暴露下层。 在一个实施例中，下层可以包括抛光特性的横向变化。 该方法可以包括使用介电层的固定研磨抛光来减少介电层下面的附加层的所需厚度。 当通过除了抛光之外的技术来期望暴露下层时，这种方法可能是有用的。

公开(公告)号：US06817903B1

公开(公告)日：2004-11-16

申请号：US09635507

申请日：2000-08-09

Applicant: Krishnaswamy Ramkumar ,  Kaichiu Wong ,  Venuka Jayatilaka

Inventor： Krishnaswamy Ramkumar ,  Kaichiu Wong ,  Venuka Jayatilaka

IPC: H01L21311

CPC classification number: H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/31662 ,  H01L21/76205 ,  H01L21/76224

Abstract: A method and process reducing or eliminating electrical leakage between active areas in a semiconductor separated by isolation regions. A method and process are disclosed for the fabrication of an isolation region in a semiconductor. The method and process can be used in the fabrication of isolation regions used for the separation of adjacent active areas in an integrated circuit. A shallow trench is created on the surface of the semiconductor in regions where isolation spaces are to be formed. A layer of silicon dioxide (LINOX) is then grown over the surfaces of the trench. The LINOX covers roughened regions formed along the surfaces of the trench during its formation. The LINOX is then annealed at a temperature above the LINOX deposition temperature for a period of time. Annealing reduces stresses in the LINOX and in the surrounding semiconductor material. Annealing also increases the density of the LINOX. Thus annealing increases the LINOX resistance to gouge during subsequent processing. This leads to a reduction in dislocations in the semiconductor and a reduction in electrical leakage around the isolation region. A more robust LINOX and a reduction in electrical leakage around an isolation region allows the further shrinkage of integrated circuit dimensions. Furthermore, denuding and gettering of the semiconductor are both accomplished during the annealing step which results in a shortening of total processing time. Finally, since gouging of the LINOX no longer occurs where poly/spacer etch overlaps an active area corner, restrictions on placement of poly lines have been eliminated.

Abstract translation: 一种减少或消除由隔离区隔开的半导体的有源区之间的漏电的方法和过程。 公开了用于制造半导体中的隔离区域的方法和工艺。 该方法和过程可用于制造用于在集成电路中分离相邻有源区的隔离区。 在要形成隔离空间的区域中，在半导体的表面上形成浅沟槽。 然后在沟槽的表面上生长一层二氧化硅（LINOX）。 LINOX包括在其形成期间沿着沟槽的表面形成的粗糙区域。 然后将LINOX在高于LINOX沉积温度的温度下退火一段时间。 退火降低了LINOX和周围半导体材料的应力。 退火也增加了LINOX的密度。 因此，退火在后续加工过程中增加了LINOX电阻。 这导致半导体中位错的减少和隔离区周围的漏电减少。 更强大的LINOX和隔离区域周围的漏电减少允许集成电路尺寸进一步收缩。 此外，半导体的剥蚀和吸杂都在退火步骤期间完成，这导致总处理时间的缩短。 最后，由于在多层/间隔层蚀刻与有源区域角重叠的情况下，LINOX的刨削不再发生，所以已经消除了对多线的布置的限制。

公开(公告)号：US06677213B1

公开(公告)日：2004-01-13

申请号：US10094108

申请日：2002-03-08

Applicant: Krishnaswamy Ramkumar ,  Frederick B. Jenne

Inventor： Krishnaswamy Ramkumar ,  Frederick B. Jenne

IPC: H01L21336

CPC classification number: H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/3003 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

Abstract: A method for processing a semiconductor topography is provided, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across one or more interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. In some embodiments, the method may include forming a deutereated nitride layer above the SONOS structure prior to the reflow process. In addition or alternatively, the method may include forming a deutereated nitride layer within the SONOS structure prior to the reflow process. In some cases, the method may further include annealing the SONOS structure with a deutereated substance prior to forming the deutereated nitride layer. In either embodiment, a SONOS structure may be formed which includes deuterium arranged within an interface of a silicon layer and an oxide layer of the structure.

Abstract translation: 提供了一种用于处理半导体形貌的方法，其包括在氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）结构的一个或多个界面上扩散氘。 特别地，该方法可以包括在SONOS结构之间隔开的电介质层的回流期间扩散氘穿过SONOS结构的一个或多个界面。 在一些实施方案中，该方法可以包括在回流工艺之前在SONOS结构之上形成去氢化氮化物层。 另外或替代地，该方法可以包括在回流工艺之前在SONOS结构内形成一个去氢化氮化物层。 在一些情况下，该方法可以进一步包括在形成去氢化氮化物层之前用缺失的物质退火SONOS结构。 在任一实施例中，可以形成SONOS结构，其包括排列在硅层和该结构的氧化物层的界面内的氘。