公开(公告)号：US20200381032A1

公开(公告)日：2020-12-03

申请号：US16770411

申请日：2018-12-10

Applicant: TOHOKU UNIVERSITY

Inventor： Hiroki KOIKE ,  Tetsuo Endoh

IPC: G11C11/16

Abstract: A storage circuit (11) includes memory cells (MCij), each of which includes an MTJ element, and reference cells (RCi), each of which includes a series circuit of an MTJ element set to a low-resistance state and a linear resistor (FR). A RW circuit (23j) that includes a sense amplifier is provided in each column of a memory cell array (21), and compares a data voltage on a corresponding bit line (BLj) with a reference voltage. The sense amplifier includes a pair of PMOS transistors to which the data voltage and the reference voltage are applied, a CMOS sense latch that is connected to a current path of the PMOS transistors.

公开(公告)号：US10741228B2

公开(公告)日：2020-08-11

申请号：US16089153

申请日：2017-03-27

Applicant: Tohoku University

Inventor： Yitao Ma ,  Tetsuo Endoh

IPC: G11C7/00 ,  G11C7/22 ,  G11C15/04 ,  G11C15/02

Abstract: A memory device capable of reading reference data while achieving optimization of electric power consumption is provided. A memory device includes a memory area storing reference data of N (≥1) dimensions each composed of M (≥1) bits. A number of memory grains each composed of nonvolatile memory and power drivers paired with the memory grains to supply electrical power to the memory grains are provided in each region specified by column lines in the number and M row lines, the number being one to N inclusive. When the power driver receives a control signal from the corresponding one of the column lines, a control signal from the corresponding one of the M row lines, and a clock signal, the power driver supplies electrical power to the memory grain in synchronization with the clock signal.

公开(公告)号：US20200211611A1

公开(公告)日：2020-07-02

申请号：US16339818

申请日：2017-10-31

Applicant: TOHOKU UNIVERSITY

Inventor： Takahiro Hanyu ,  Daisuke Suzuki ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C11/16 ,  H01L43/02

Abstract: A data write device for a resistive memory element, the resistive memory element including: a conductive electrode provided at one end of the memory element; and a reading electrode provided at the other end of the memory element being configured to vary a resistance of the memory element by applying a write current to the conductive electrode, the data write device for the resistive memory element further includes: a writing means, an output means, and a control means. The output means is provided between a power supply and the reading electrode. As output signals, a read signal from the memory element and a monitor signal to monitor a writing status of the memory element written by the writing means are output from the output means. By the monitor signal, a termination of data-writing into the resistive memory element is detected.

公开(公告)号：US10658572B2

公开(公告)日：2020-05-19

申请号：US16179461

申请日：2018-11-02

Applicant: TOHOKU UNIVERSITY

Inventor： Hideo Sato ,  Shoji Ikeda ,  Mathias Bersweiler ,  Hiroaki Honjo ,  Kyota Watanabe ,  Shunsuke Fukami ,  Fumihiro Matsukura ,  Kenchi Ito ,  Masaaki Niwa ,  Tetsuo Endoh ,  Hideo Ohno

IPC: H01L43/08 ,  H01L27/22 ,  H01F10/16 ,  H01F10/32 ,  H01L27/105 ,  H01L29/82 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetoresistance effect element includes first and second magnetic layers having a perpendicular magnetization direction, and a first non-magnetic layer disposed adjacent to the first magnetic layer and on a side opposite to a side on which the second magnetic layer is disposed. An interfacial perpendicular magnetic anisotropy exists at an interface between the first magnetic layer and the first non-magnetic layer, and the anisotropy causes the first magnetic layer to have a magnetization direction perpendicular to the surface of the layers. An atomic fraction of all magnetic elements to all magnetic and non-magnetic elements included in the second magnetic layer is smaller than that of the first magnetic layer.

公开(公告)号：US20190371370A1

公开(公告)日：2019-12-05

申请号：US16466812

申请日：2017-12-18

Applicant: Tohoku University

Inventor： Takahiro Hanyu ,  Daisuke Suzuki ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C7/06 ,  G11C16/26

Abstract: In reading of a memory unit, an read failure operation due to variation in characteristic of a transistor in a dynamic load is reduced. A read circuit that reads a voltage obtained by a voltage division of a dynamic load unit and the memory unit as an output of the memory unit includes the dynamic load unit having one end connected to a side of a power supply and the other end connected to a side of the memory unit, and a feedback unit that, by a feedback of the voltage obtained by the voltage division that is divided between the dynamic load unit and the memory unit, holds the voltage obtained by the voltage division. The dynamic load unit has an array structure in which a plurality of resistive memory elements are connected in series, in parallel, or in series-parallel. The dynamic load unit has the array structure of the resistive memory elements and this structure can suppress the read failure operation due to the variation in dynamic load.

公开(公告)号：US20190304741A1

公开(公告)日：2019-10-03

申请号：US16360516

申请日：2019-03-21

Applicant: Tohoku University ,  Toray Research Center, Inc.

Inventor： Masaaki Niwa ,  Tetsuo Endoh ,  Shoji Ikeda ,  Kosuke Kimura

IPC: H01J37/22 ,  G01N23/20091 ,  H01J37/28

Abstract: An evaluation method for an electronic device provided with an insulating film between a pair of electrode layers includes preparing a sample that has a tunnel barrier insulating film as the insulating film; irradiating the sample with electron beams from a plurality of angles to acquire a plurality of images; and performing image processing using the plurality of images to reconstruct a stereoscopic image and generate a cross-sectional image of the sample from the stereoscopic image.

公开(公告)号：US20190221262A1

公开(公告)日：2019-07-18

申请号：US16099966

申请日：2017-05-11

Applicant: Tohoku University

Inventor： Yitao Ma ,  Tetsuo Endoh

IPC: G11C15/04 ,  G06F16/903 ,  G06K9/62

CPC classification number: G11C15/04 ,  G06F12/00 ,  G06F16/90339 ,  G06K9/6276 ,  G11C5/14 ,  G11C14/00

Abstract: A memory device and a memory system capable of flexibly corresponding to the number of dimensions of reference data and having a compact circuit configuration at searching for data similar to search data are provided. A memory system capable of reducing processing time to search for data similar to search data and reducing a circuit area is provided. A memory device includes a plurality of read circuits, an input search data storing circuit configured to divide search data to output, a plurality of similarity evaluation cells and a plurality of current accumulators. The memory system is configured by including a main core and a branch core thus configured.

公开(公告)号：US20190189917A1

公开(公告)日：2019-06-20

申请号：US16328852

申请日：2017-03-21

Applicant: TOHOKU UNIVERSITY

Inventor： Hiroaki Honjo ,  Tetsuo Endoh ,  Shoji Ikeda ,  Hideo Sato ,  Hideo Ohno

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetic tunnel junction element includes, in a following stack order, an underlayer formed of a metal material, a fixed layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, and a recording layer formed of a ferromagnetic body, or alternatively, the magnetic tunnel junction element includes, in a following stack order, a recording layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, an underlayer formed of a metal material, and a fixed layer formed of a ferromagnetic body, wherein the fixed layer is formed and stacked after performing plasma treatment to a surface of the underlayer having been formed.

公开(公告)号：US09941468B2

公开(公告)日：2018-04-10

申请号：US15502442

申请日：2015-07-29

Applicant: TOHOKU UNIVERSITY

Inventor： Shunsuke Fukami ,  Chaoling Zhang ,  Tetsuro Anekawa ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C11/00 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H01L27/105 ,  H01L27/228 ,  H01L29/82 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetoresistance effect element (100) includes a heavy metal layer (11) that includes a heavy metal and that is formed to extend in a first direction, a recording layer (12) that includes a ferromagnetic material and that is provided adjacent to the heavy metal layer (11), a barrier layer (13) that includes an insulating material and that is provided on the recording layer (12) with being adjacent to a surface of the recording layer (12) opposite to the heavy metal layer (11), and a reference layer (14) that includes a ferromagnetic material and that is provided adjacent to a surface of the barrier layer (13), the surface being opposite to the recording layer (12). The direction of the magnetization of the reference layer (14) has a component substantially fixed in the first direction, and the direction of the magnetization of the recording layer (12) has a component variable in the first direction. A current having a direction same as the first direction is introduced to the heavy metal layer (11) to thereby enable the magnetization of the recording layer (12) to be inverted.

公开(公告)号：US09928906B2

公开(公告)日：2018-03-27

申请号：US15128020

申请日：2015-03-24

Applicant: TOHOKU UNIVERSITY

Inventor： Takahiro Hanyu ,  Daisuke Suzuki ,  Masanori Natsui ,  Akira Mochizuki ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0064 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0083

Abstract: A data-write device includes a write driver that causes a current to flow through a current path including an MTJ element or the other current path including the MTJ element in accordance with writing data to be written, thereby writing the write data into the MTJ element, a write completion detector which monitors the voltage at a first connection node or a second connection node in accordance with the write data after the writing of the write data into the MTJ element starts, detects the completion of writing of the write data based on the voltage at either node, and supplies a write completion signal indicating the completion of data write, and a write controller that terminates the writing of the write data into the MTJ element in response to the write completion signal supplied from the write completion detector.