公开(公告)号：US11735648B2

公开(公告)日：2023-08-22

申请号：US17324512

申请日：2021-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/66803 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L21/845 ,  H01L29/66545

Abstract: A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.

公开(公告)号：US20230215761A1

公开(公告)日：2023-07-06

申请号：US18178773

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chen Wang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chia-Ta Yu ,  Han-Jong Chia

IPC: H01L21/768 ,  H01L29/24 ,  H01L23/532 ,  H01L21/02 ,  H01L23/522 ,  H10B51/20 ,  H10B51/30

CPC classification number: H01L21/7682 ,  H01L29/24 ,  H01L21/76877 ,  H01L23/5329 ,  H01L21/02565 ,  H01L21/76802 ,  H01L23/5226 ,  H10B51/20 ,  H10B51/30

Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

公开(公告)号：US20230008998A1

公开(公告)日：2023-01-12

申请号：US17567269

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi On Chui ,  Sheng-Chen Wang

IPC: H01L27/11597 ,  H01L27/11514 ,  G11C5/06 ,  H01L29/78 ,  H01L29/66

Abstract: In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.

公开(公告)号：US20220384347A1

公开(公告)日：2022-12-01

申请号：US17818562

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L23/535 ,  H01L27/1159 ,  H01L27/11597

Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

公开(公告)号：US20220367516A1

公开(公告)日：2022-11-17

申请号：US17874815

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Chung-Te Lin ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang

IPC: H01L27/11597 ,  H01L27/1159 ,  G11C11/56

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

公开(公告)号：US20220366952A1

公开(公告)日：2022-11-17

申请号：US17814341

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: G11C8/14 ,  H01L21/822 ,  H01L21/8239 ,  H01L27/105 ,  H01L27/11597

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

公开(公告)号：US11495618B2

公开(公告)日：2022-11-08

申请号：US17112606

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L23/522 ,  H01L27/1159 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/11578

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US11476352B2

公开(公告)日：2022-10-18

申请号：US17121007

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/265 ,  H01L21/225 ,  H01L29/66 ,  H01L29/165

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US11407083B2

公开(公告)日：2022-08-09

申请号：US16449855

申请日：2019-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Bin Hsu ,  Ren-Guei Lin ,  Feng-Inn Wu ,  Sheng-Chen Wang ,  Jung-Yu Li

IPC: B24B37/26 ,  B24B57/02 ,  B24B49/10 ,  B24B49/00 ,  B24B49/16

Abstract: A method includes supplying slurry onto a polishing pad. A wafer is held against the polishing pad with a first piezoelectric layer interposed between a pressure unit and the wafer. A first voltage generated by the first piezoelectric layer is detected. The wafer is pressed, using the pressure unit, against the polishing pad according to the detected first voltage generated by the first piezoelectric layer. The wafer is polished using the polishing pad.

公开(公告)号：US20220037362A1

公开(公告)日：2022-02-03

申请号：US17140888

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/1159

Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.