公开(公告)号：US06903423B2

公开(公告)日：2005-06-07

申请号：US10843318

申请日：2004-05-12

申请人： Helmut Fischer ,  Jens Egerer

发明人： Helmut Fischer ,  Jens Egerer

IPC分类号： G11C5/14 ,  G11C11/407 ,  G11C29/00 ,  G11C29/02 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： G11C29/02 ,  G11C2029/5006

摘要： An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.

摘要翻译： 集成半导体存储器可以包括布置在非重叠区域部分上的多个子电路块。 每个子电路块具有块供电线和块接地线，其为电路中的各个电路块的各个开关元件提供电压。 每个块供电线和块接地线连接到芯片供电线和芯片接地线，其在子电路块的区域外延伸。 至少一个子电路块的芯片供给线和块供应线之间或至少一个子电路块的芯片接地线和块接地线之间的至少一个连接可以由开关器件隔离。 此外，一种减少半导体存储器中漏电流的方法，其取决于半导体存储器的工作状态，将半导体存储器的各个子电路块与电压源隔离或连接。

公开(公告)号：US20050002245A1

公开(公告)日：2005-01-06

申请号：US10850817

申请日：2004-05-21

申请人： Ruediger Brede ,  Dominique Savignac ,  Helmut Fischer

发明人： Ruediger Brede ,  Dominique Savignac ,  Helmut Fischer

IPC分类号： G11C7/10 ,  G11C11/4076 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/028 ,  G11C7/1045 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/50 ,  G11C29/50012

摘要： In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration. Then information on the modified default time duration or on the ascertained real time duration are stored in the memory element during the test operation mode, wherein the second operation is executed offset by the modified default time duration after the execution instant of the first operation during the normal operation mode.

摘要翻译： 在用于修改第二操作的执行时刻和先前在存储元件中执行的第一操作的较早执行时刻之间的默认持续时间的方法中，其中该存储元件可在测试操作模式和正常操作模式下操作， 首先，在测试操作模式期间确定和提供存储器元件中的实时持续时间，其中选择实时持续时间，使得当使用第一时钟的执行时刻之间的实时持续时间时，存储器元件的性能参数 并且第二操作改进了使用第一操作和第二操作的执行时刻之间的默认持续时间的情况。 然后，在测试操作模式期间，在实时持续时间的方向上改变默认持续时间，以获得修改的默认持续时间。 然后，在测试操作模式期间将关于修改的默认持续时间或所确定的实时持续时间的信息存储在存储器元件中，其中第二操作被执行偏移了在第一操作期间的执行时刻之后的修改的默认持续时间 正常运行模式。

公开(公告)号：US06787801B2

公开(公告)日：2004-09-07

申请号：US10247574

申请日：2002-09-19

申请人： Helmut Fischer ,  Alan Morgan

发明人： Helmut Fischer ,  Alan Morgan

IPC分类号： H01L2358

CPC分类号： H01L22/32 ,  G01R31/2884 ,  G11C29/006 ,  G11C29/48 ,  G11C2029/1206

摘要： Integrated circuits are tested on the wafer level through an additional circuit part that is electrically connected via at least one connecting line with the associated integrated circuit. The additional circuit part is integrated into an interspace between the integrated circuits of the wafer. Functions of the integrated circuit can be controlled via the connecting line. For example, in the case of a memory module such as a DRAM, internal voltages and/or currents of the integrated circuit can advantageously be measured even on internal lines which are otherwise only accessible with difficulty. Following the wafer-level testing and dicing of the integrated circuits into individual chips, the additional circuit part becomes unusable.

摘要翻译： 通过经由至少一个连接线与相关联的集成电路电连接的附加电路部件在晶片级上测试集成电路。 附加电路部分集成在晶片的集成电路之间的间隙中。 集成电路的功能可以通过连接线控制。 例如，在诸如DRAM的存储器模块的情况下，集成电路的内部电压和/或电流即使在内部线路上也可以有利地被测量，否则这些线路将难以进入。 在将晶圆级测试和集成电路切割成单个芯片之后，附加电路部分变得不可用。

公开(公告)号：US06768139B2

公开(公告)日：2004-07-27

申请号：US10217184

申请日：2002-08-12

申请人： Helmut Fischer ,  Jürgen Lindolf

发明人： Helmut Fischer ,  Jürgen Lindolf

IPC分类号： H01L31072

CPC分类号： G05F3/30 ,  H01L29/7327

摘要： A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type well, is used as a base terminal. The n-type well constitutes the emitter terminal. A negatively doped region, which acts as a collector terminal, is formed in the p-type well. The structure that is used exists in DRAM processes, and it can therefore be used to form an npn transistor as a footprint diode in bandgap circuits.

摘要翻译： 用于带隙电路的晶体管配置被配置为npn晶体管的形式。 被埋置的n型阱包围的绝缘p型阱用作基极端子。 n型阱构成发射极端子。 在p型阱中形成用作集电极端子的负掺杂区域。 所使用的结构存在于DRAM工艺中，因此可用于在带隙电路中形成npn晶体管作为覆盖二极管。

公开(公告)号：US06738309B2

公开(公告)日：2004-05-18

申请号：US10154597

申请日：2002-05-23

申请人： Alexander Benedix ,  Kazimierz Szczypinski ,  Helmut Fischer ,  Johann Pfeiffer

发明人： Alexander Benedix ,  Kazimierz Szczypinski ,  Helmut Fischer ,  Johann Pfeiffer

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222

摘要： A semiconductor memory is described which has a clock input, a signal input, a data output, a measuring device, a control circuit, and a latency. The latency elapses between the activation of the signal input and the availability of the data to be read at the data output. A clock signal is fed to the clock input. On the basis of the clock signal, the measuring device determines a value for the latency and the control circuit configures the semiconductor memory with the determined value for the operation of the semiconductor memory.

摘要翻译： 描述了具有时钟输入，信号输入，数据输出，测量装置，控制电路和等待时间的半导体存储器。 在信号输入的激活和在数据输出端要读取的数据的可用性之间经过了延迟。 时钟信号被馈送到时钟输入。 基于时钟信号，测量装置确定延迟的值，并且控制电路以半导体存储器的操作的确定值配置半导体存储器。

公开(公告)号：US06665228B2

公开(公告)日：2003-12-16

申请号：US10166962

申请日：2002-06-11

申请人： Alexander Benedix ,  Sebastian Kuhne ,  Helmut Fischer ,  Bernd Klehn ,  Helmut Schneider

发明人： Alexander Benedix ,  Sebastian Kuhne ,  Helmut Fischer ,  Bernd Klehn ,  Helmut Schneider

IPC分类号： G11C800

CPC分类号： G11C11/4087 ,  G11C8/14

摘要： An integrated memory has a memory cell array, which is subdivided into a plurality of separate segments. A first and a second local word line in different segments together form a common global word line. The global word line is decoded via a row decoder. The first and second local word lines are connected to a column decoder in such a way that they can be decoded individually and segment by segment in a manner dependent on a column address. The memory thus allows fast and current-saving activation of a word line.

公开(公告)号：US06507528B2

公开(公告)日：2003-01-14

申请号：US09981855

申请日：2001-10-18

申请人： Ioannis Chrissostomidis ,  Thilo Schaffroth ,  Helmut Fischer

发明人： Ioannis Chrissostomidis ,  Thilo Schaffroth ,  Helmut Fischer

IPC分类号： G11C700

CPC分类号： G11C7/06

摘要： A circuit configuration for generating sense amplifier control signals for a DRAM. The circuit configuration includes, in addition to thin oxide transistors that are supplied with a normal standard supply voltage, thick oxide transistors to which an increased supply voltage is applied to compensate for voltage and technological fluctuations.

公开(公告)号：US06477106B2

公开(公告)日：2002-11-05

申请号：US09925170

申请日：2001-08-08

申请人： Helmut Fischer ,  Joachim Schnabel

发明人： Helmut Fischer ,  Joachim Schnabel

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C8/00

摘要： A circuit configuration for deactivating word lines in a memory matrix. The circuit configuration contains controllable connection devices for connecting the relevant word line to a common supply line system carrying the deactivation potential for the word lines. The circuit configuration contains a control circuit that, in response to a deactivation command, produces a deactivation control signal that turns on the controllable connection devices. A reduction device is provided which can be switched on selectively and which, when switched on, limits the currents flowing through the turned-on connection devices to such an extent that the total current flowing via the supply line system does not exceed a prescribed value.

公开(公告)号：US06407586B2

公开(公告)日：2002-06-18

申请号：US09781813

申请日：2001-02-12

申请人： Helmut Fischer ,  Jochen Müller

发明人： Helmut Fischer ,  Jochen Müller

IPC分类号： H03K1900

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a fusible link configuration in or on integrated circuits, in particular highly integrated memory chips, in which in each case one bank of fusible links (F1, F2, . . . ), together with an evaluation logic unit is configured beside and in association with a memory field segment. The evaluation logic unit is electrically connected to the fusible links (F1, F2, . . . ) and determines whether one or more of the fusible links (F1, F2, . . . ) is severed. One or more banks of the fusible links (F1, F2, . . . ) are divided up into smaller units while restricting the width(s) of the bank or banks. The units are grouped such that at least some of the fusible links (F1, F2, . . . ) are located beside one another transversely with respect to the width direction of the bank.

摘要翻译： 本发明涉及集成电路中或其上的可熔链路配置，特别是高度集成的存储器芯片，其中在每种情况下，一组可熔链路（F1，F2，...）以及评估逻辑单元被配置在旁边 并且与存储器区段相关联。 评估逻辑单元电连接到可熔链路（F1，F2 ...），并确定是否断开了一个或多个可熔链路（F1，F2 ...）。 一个或多个可熔链节（F1，F2 ...）被划分成更小的单位，同时限制银行或银行的宽度。 这些单元被分组成使得至少一些可熔链节（F1，F2 ...）相对于堤的宽度方向横向彼此相邻。

公开(公告)号：US4896520A

公开(公告)日：1990-01-30

申请号：US237383

申请日：1988-08-29

申请人： Ulrich Bruhnke ,  Helmut Fischer ,  Matthias Schwarz ,  Erwin Uecker ,  Reinhard Wittwer

发明人： Ulrich Bruhnke ,  Helmut Fischer ,  Matthias Schwarz ,  Erwin Uecker ,  Reinhard Wittwer

IPC分类号： E05B13/00 ,  E05B53/00 ,  E05B77/50 ,  E05B79/20 ,  E05B83/30

CPC分类号： E05B13/005 ,  E05B79/20 ,  E05B77/50 ,  E05B83/30 ,  Y10T70/5124 ,  Y10T70/5544 ,  Y10T70/5973

摘要： The invention relates to a lockable glove and auxiliary compartment cover system for motor cars having a lock which is transferable into its tripping position by the stressing of a tripping lever by means of an actuating element. A closing member is provided which can be rotated between positions permitting and blocking the operative connection between the actuating element and the lock to change the security condition of the system. The change of the security condition occurs by means of a toothed-wheel gear which comprises a spur gear element rotatable with the closing element and a further gear element meshing with the spur gear element. In order to permit a handier arrangement of the actuating elements, the further gear element is likewise constructed as a rotatably mounted spur gear element, at least one of the spur gear elements, which belongs to a push-button, is guided for axial sliding, and a tripping stud protrudes eccentrically from the spur gear elements guided for axial sliding by means of which the tripping lever is pivotable in order to trip the lock.

摘要翻译： 本发明涉及一种用于机动车辆的可锁定手套和辅助舱盖系统，其具有通过致动元件对脱扣杆的应力可转移到其脱扣位置的锁。 提供闭合构件，其可以在允许和阻止致动元件和锁之间的操作连接的位置之间旋转以改变系统的安全状态。 安全条件的改变是通过齿轮齿轮发生的，该齿轮包括可与闭合元件一起旋转的正齿轮元件和与正齿轮元件啮合的另一个齿轮元件。 为了允许致动元件的更方便的布置，另外的齿轮元件同样被构造为可旋转地安装的正齿轮元件，属于按钮的至少一个正齿轮元件被引导用于轴向滑动， 并且跳闸螺栓从被引导用于轴向滑动的正齿轮元件偏心地突出，通过该螺栓将脱扣杆可枢转以便跳闸。