公开(公告)号：US20080157314A1

公开(公告)日：2008-07-03

申请号：US11619196

申请日：2007-01-03

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Michael C. Gaidis ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Michael C. Gaidis ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L23/02

CPC分类号： H01L23/576 ,  H01L21/31144 ,  H01L23/544 ,  H01L28/20 ,  H01L28/40 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.

摘要翻译： 一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机 结构纳米孔特征。 在无规纳米孔结构化中间层上形成上导电层。 上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

公开(公告)号：US20080156265A1

公开(公告)日：2008-07-03

申请号：US12047561

申请日：2008-03-13

申请人： Keith Kwong Hon Wong ,  Robert J. Purtell

发明人： Keith Kwong Hon Wong ,  Robert J. Purtell

IPC分类号： C23C16/06

CPC分类号： H01L21/28518 ,  C23C14/16 ,  C23C14/32 ,  C23C14/345 ,  H01L21/28052 ,  H01L21/2855 ,  H01L29/66507 ,  H01L29/78

摘要： A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.

公开(公告)号：US07394332B2

公开(公告)日：2008-07-01

申请号：US11217163

申请日：2005-09-01

申请人： Louis C. Hsu ,  Lowrence A. Clevenger ,  Timothy J. Dalton ,  Carl J. Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Louis C. Hsu ,  Lowrence A. Clevenger ,  Timothy J. Dalton ,  Carl J. Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01P1/10

CPC分类号： H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

摘要： A MEM switch is described having a free moving element within in micro-cavity, and guided by at least one inductive element. The switch consists of an upper inductive coil; an optional lower inductive coil, each having a metallic core preferably made of permalloy; a micro-cavity; and a free-moving switching element preferably also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When the chip is not mounted with the correct orientation, gravity cannot be used. In such an instance, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.

摘要翻译： 描述了一种MEM开关，其具有在微腔内的自由移动元件，并由至少一个电感元件引导。 开关由上感应线圈组成; 可选的下感应线圈，每个具有优选由坡莫合金制成的金属芯; 微腔; 以及优选也由磁性材料制成的自由移动的开关元件。 通过使电流通过上部线圈来实现切换，从而在线圈元件中产生磁场。 磁场向上吸引自由移动的磁性元件，短路两根开放的电线，从而闭合开关。 当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且电线打开。 当芯片未正确安装时，重力不能使用。 在这种情况下，需要下部线圈将自由移动的开关元件拉回并将其保持在其原始位置。

公开(公告)号：US20080138985A1

公开(公告)日：2008-06-12

申请号：US11567517

申请日：2006-12-06

申请人： Anita Madan ,  Robert J. Purtell ,  Keith Kwong Hon Wong ,  Jun-Keun Kwak

发明人： Anita Madan ,  Robert J. Purtell ,  Keith Kwong Hon Wong ,  Jun-Keun Kwak

IPC分类号： H01L21/44

CPC分类号： H01L21/28518

摘要： A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at an initial degas temperature of about 250 to about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a nickel containing layer over the wafer following transfer of the wafer from the degas chamber to the deposition chamber, and annealing the semiconductor wafer so as to create silicide regions at portions on the wafer where nickel material is formed over silicon.

摘要翻译： 形成用于半导体器件的硅化物触点的方法包括在约250至约400℃的初始脱气温度下对含硅半导体晶片进行脱气处理，将半导体晶片从脱气室转移至沉积室， 将晶片从脱气室转移到沉积室之后，在晶片上方的镍含量层，以及对半导体晶片进行退火，以在晶片上形成硅材料的部分上形成硅化物区域，其中镍材料形成在硅上。

公开(公告)号：US20080020488A1

公开(公告)日：2008-01-24

申请号：US11488242

申请日：2006-07-18

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/00

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面上的高Q片上电感器，并且使用晶片间互连连接到芯片前端的集成电路。 例如，具有背面集成电感器的半导体器件包括半导体衬底，其具有插入在衬底的前侧和后侧之间的前侧，后侧和掩埋绝缘层。 在半导体衬底的前侧形成集成电路，在半导体衬底的背面形成集成电感器。 通过埋层绝缘层形成互连结构，将集成电感器连接到集成电路。 半导体衬底可以是SOI（绝缘体上硅）结构。

公开(公告)号：US06916729B2

公开(公告)日：2005-07-12

申请号：US10409516

申请日：2003-04-08

申请人： Sunfei Fang ,  Keith Kwong Hon Wong ,  Paul D. Agnello ,  Christian Lavoie ,  Lawrence A. Clevenger ,  Chester T. Dziobkowski ,  Richard J. Murphy ,  Patrick W. DeHaven ,  Nivo Rovedo ,  Hsiang-Jen Huang

发明人： Sunfei Fang ,  Keith Kwong Hon Wong ,  Paul D. Agnello ,  Christian Lavoie ,  Lawrence A. Clevenger ,  Chester T. Dziobkowski ,  Richard J. Murphy ,  Patrick W. DeHaven ,  Nivo Rovedo ,  Hsiang-Jen Huang

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

摘要： A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

摘要翻译： 在半导体器件上形成硅化物的方法包括在衬底的硅区域上沉积第一难熔金属层，在第一耐火金属层上沉积近贵金属层，以及在第二耐火金属层的近旁沉积第二难熔金属层， 贵金属层。 半导体器件在第一退火工艺中退火以形成邻接半导体器件的掺杂区域的硅化物层。 除去近贵金属层和第二难熔金属层的未反应部分。 该器件可以在任选的第二退火工艺中进行退火，以将硅化物层转换成低电阻相位硅化物材料。 通过本发明的实施例使结漏电和桥接最小化或消除，并且实现更平滑的硅化表面。

公开(公告)号：US06794262B2

公开(公告)日：2004-09-21

申请号：US10252476

申请日：2002-09-23

申请人： Xian J. Ning ,  Keith Kwong Hon Wong

发明人： Xian J. Ning ,  Keith Kwong Hon Wong

IPC分类号： H01L2120

CPC分类号： H01L28/86 ,  H01L21/31604 ,  H01L21/76807 ,  H01L23/5223 ,  H01L28/55 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-insulator-metal (MIM) capacitor (242/252) structure and method of forming the same. A dielectric layer (214) of a semiconductor device (200) is patterned with a dual damascene pattern having a first pattern (216) and a second pattern (218). The second pattern (218) has a greater depth than the first pattern (216). A conductive layer (226) is formed over the dielectric layer (214) in the first pattern, and a conductive layer is formed over the conductive layer in the first pattern (216). A dielectric layer (232), conductive layer (234), dielectric layer (236) and conductive layer (238) are disposed over the conductive layer (226) of the second pattern (218). Conductive layer (234), dielectric layer (232) and conductive layer (226) form a first MIM capacitor (252). Conductive layer (238), dielectric layer (236) and conductive layer (234) form a second MIM capacitor (242) parallel to the first MIM capacitor (242).

公开(公告)号：US09184214B2

公开(公告)日：2015-11-10

申请号：US13083893

申请日：2011-04-11

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Keith Kwong Hon Wong

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Keith Kwong Hon Wong

IPC分类号： H01L21/02 ,  H01L27/24

CPC分类号： H01L29/518 ,  H01L27/24 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.

摘要翻译： 半导体器件包括衬底和设置在衬底上的栅极堆叠。 栅极堆叠的上层是金属栅极导体，栅极叠层的下层是栅极电介质。 栅极触点与金属栅极导体直接接触。

公开(公告)号：US08946028B2

公开(公告)日：2015-02-03

申请号：US12574296

申请日：2009-10-06

申请人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang ,  Keith Kwong Hon Wong

发明人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： FinFETs are merged together by a metal. The method of manufacturing the FinFETs include forming a plurality of fin bodies on a substrate and merging the fin bodies with a metal. The method further includes implanting source and drain regions through the metal.

摘要翻译： FinFET由金属合并在一起。 制造FinFET的方法包括在基板上形成多个翅片体并将金属体与翅片体合并。 该方法还包括通过金属注入源区和漏区。

公开(公告)号：US08546209B1

公开(公告)日：2013-10-01

申请号：US13524576

申请日：2012-06-15

申请人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a semiconductor device structure includes forming an interlevel dielectric (ILD) layer over a semiconductor substrate and a dummy transistor gate structure formed on the substrate; infusing a shallow gas cluster ion beam (GCIB) layer in a top portion of the ILD layer; and removing at least one layer from the dummy transistor gate structure, wherein the at least one layer comprises a same material as the ILD layer and wherein the GCIB layer has a slower etch rate with respect to the ILD layer.

摘要翻译： 形成半导体器件结构的方法包括在半导体衬底上形成层间电介质（ILD）层，以及在衬底上形成的虚设晶体管栅极结构; 在浅层气体簇离子束（GCIB）层中注入ILD层的顶部; 以及从所述虚拟晶体管栅极结构去除至少一个层，其中所述至少一个层包含与所述ILD层相同的材料，并且其中所述GCIB层相对于所述ILD层具有较慢的蚀刻速率。