公开(公告)号：US06789248B1

公开(公告)日：2004-09-07

申请号：US10178401

申请日：2002-06-24

Applicant: Lee-Chung Lu ,  Cliff Hou ,  Chia-Lin Cheng ,  Chung-Hsing Wang ,  Hsing-Chien Huang ,  Yee-Wen Chen ,  Tsui-Ping Wang

Inventor： Lee-Chung Lu ,  Cliff Hou ,  Chia-Lin Cheng ,  Chung-Hsing Wang ,  Hsing-Chien Huang ,  Yee-Wen Chen ,  Tsui-Ping Wang

IPC: G06F1750

CPC classification number: G06F17/5068

Abstract: A method and system for the design of an electronic device adjusts the resistance and capacitance values employed in preliminary timing analysis during physical synthesis of the electronic device. The physical synthesis uses resistance and capacitance unit values to determine the listing of the component circuits. The resistance and capacitance unit values are calibrated by preliminarily placing the initially synthesized component circuits to create a listing describing physical locations of the component circuits within the electronic device. A preliminary routing of the interconnections is performed to create a listing describing a network of physical wire segments that form each interconnection of the component circuits. A timing analysis of the electronic device determines the delay created by the component circuit and the networks of physical wire segments. The time delay resulting from the physical interconnects is extracted from the timing analysis of the electronic device and from the timing estimate performed during the physical synthesis. The time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis is then compared. The resistance and capacitance unit values used during the timing synthesis are then adjusted. The calibration is repeatedly executed until time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis are correlated.

Abstract translation: 用于设计电子设备的方法和系统调节在电子设备的物理合成期间的初步时序分析中使用的电阻和电容值。 物理合成使用电阻和电容单位值来确定元件电路的列表。 电阻和电容单位值通过预先放置最初合成的组件电路来校准，以创建描述电子设备内的组件电路的物理位置的列表。 执行互连的初步路由以创建描述形成组件电路的每个互连的物理线段的网络的列表。 电子设备的定时分析确定由组件电路和物理线段网络产生的延迟。 从物理互连产生的时间延迟从电子设备的定时分析以及在物理合成期间执行的定时估计提取。 然后对来自定时分析的物理互连的时间延迟和在物理合成期间执行的定时估计进行比较。 然后调整在定时合成期间使用的电阻和电容单位值。 重复执行校准，直到来自定时分析的物理互连的时间延迟和在物理合成期间执行的定时估计相关。

公开(公告)号：US06737362B1

公开(公告)日：2004-05-18

申请号：US10377568

申请日：2003-02-28

Applicant: Chia Lin Chen ,  Chun-Lin Wu ,  Chi-Chun Chen ,  Tze Liang Lee ,  Shih-Chang Chen

Inventor： Chia Lin Chen ,  Chun-Lin Wu ,  Chi-Chun Chen ,  Tze Liang Lee ,  Shih-Chang Chen

IPC: H01L213105

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

Abstract: The present disclosure provides a method for forming a gate stack structure for semiconductor devices. The disclosed method comprises steps such as forming a dielectric layer on a substrate; applying a plasma nitridation process on the formed dielectric layer; applying a first anneal process on the deposited dielectric layer; etching the dielectric layer to a predetermined thickness using a diluted etchant; applying a second anneal process using an oxygen environment on the etched dielectric layer after the etching; and forming a gate electrode layer on top of the dielectric layer. The etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so as the leakage current is significantly reduced.

Abstract translation: 本公开提供了一种用于形成半导体器件的栅极堆叠结构的方法。 所公开的方法包括在衬底上形成介电层的步骤; 在形成的介电层上施加等离子体氮化处理; 在沉积的介电层上施加第一退火工艺; 使用稀释的蚀刻剂将介电层蚀刻到预定厚度; 在蚀刻后在蚀刻的电介质层上使用氧气环境进行第二退火处理; 以及在所述电介质层的顶部上形成栅电极层。 蚀刻使得蚀刻的电介质层的顶部具有比蚀刻的电介质层的下部显着更高的氮浓度，因此泄漏电流显着降低。

公开(公告)号：US06638830B1

公开(公告)日：2003-10-28

申请号：US10065104

申请日：2002-09-18

Applicant: Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng

Inventor： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng

IPC: H01L2120

CPC classification number: H01L28/91 ,  H01L21/31604 ,  H01L21/3162 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a high-density capacitor. At least one first trench is formed in a dielectric layer positioned on a semiconductor substrate. A first liner layer and a first conductive layer are formed on the semiconductor substrate followed by a first planarization process. At least one second trench having a joint side wall with the first trench is formed in the dielectric layer. A capacitor dielectric layer, a second liner layer, and a second conductive layer are formed on the semiconductor substrate followed by a second planarization process. The surfaces of the first conductive layer and the second conductive layer are then exposed to form a high-density capacitor having a three-dimensional structure.

Abstract translation: 一种制造高密度电容器的方法。 至少一个第一沟槽形成在位于半导体衬底上的电介质层中。 在半导体衬底上形成第一衬里层和第一导电层，接着进行第一平面化处理。 在电介质层中形成具有与第一沟槽的接合侧壁的至少一个第二沟槽。 在半导体衬底上形成电容器电介质层，第二衬垫层和第二导电层，接着进行第二平面化处理。 然后将第一导电层和第二导电层的表面暴露以形成具有三维结构的高密度电容器。

公开(公告)号：US06593185B1

公开(公告)日：2003-07-15

申请号：US10150385

申请日：2002-05-17

Applicant: Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng ,  Yi-Hsiung Lin

Inventor： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng ,  Yi-Hsiung Lin

IPC: H01L218242

CPC classification number: H01L27/108 ,  H01L28/90

Abstract: A method for fabricating a vertical three-dimensional metal-insulator-metal capacitor (MIM capacitor) structure is disclosed. The present invention utilized a vertical three-dimensional MIM capacitor structure on the substrate to decrease the structure area of the MIM capacitor in logic integrated circuit and integration for copper dual damascene process at an identical capacitance on a chip; therefore, the capacitance density of the vertical three-dimensional capacitor can be increased. Furthermore, the present invention is provided a method for fabricating the vertical three-dimensional MIM capacitor structure that compatible with the fabrication of the copper dual damascene structure such that the number of the photomask during the fabrication process can be reduced.

Abstract translation: 公开了一种用于制造垂直三维金属 - 绝缘体 - 金属电容器（MIM电容器）结构的方法。 本发明在衬底上利用垂直三维MIM电容器结构，以降低逻辑集成电路中MIM电容器的结构面积，并在芯片上的相同电容下对铜双镶嵌工艺进行集成; 因此，可以增加垂直三维电容器的电容密度。 此外，本发明提供一种制造与铜双镶嵌结构的制造兼容的垂直三维MIM电容器结构的方法，使得可以减少在制造过程中的光掩模的数量。

公开(公告)号：US06587026B2

公开(公告)日：2003-07-01

申请号：US09941625

申请日：2001-08-30

Applicant: Ming Yeh ,  Heng Cheng Chou ,  Chen-Feng Wu ,  Hui-Hua Teng ,  Chien-Chia Lin

Inventor： Ming Yeh ,  Heng Cheng Chou ,  Chen-Feng Wu ,  Hui-Hua Teng ,  Chien-Chia Lin

IPC: H01F500

CPC classification number: H01F27/2804 ,  H05K1/165

Abstract: An embedded transformer embedded in a board is disclosed. The embedded transformer includes a board, a first insulating sheet, a preformed coil, a second insulating sheet, a first core and a second core. Among these, the board includes a conductive pattern formed on an upper surface of the board. A part of said conductive pattern serves as a primary coil of the embedded transformer. The first insulating sheet is formed on the conductive pattern. The preformed coil is formed on the first insulating sheet. The second insulating sheet is formed on the preformed coil. The first core is formed on the second insulating sheet and partially embedded in the board. The second core formed on a lower surface of the board is partially embedded in the board so as to be couple to the first core.

公开(公告)号：US06583031B2

公开(公告)日：2003-06-24

申请号：US09915217

申请日：2001-07-25

Applicant: Chuang-Chia Lin

Inventor： Chuang-Chia Lin

IPC: H01L2130

CPC classification number: G02B6/3518 ,  B81B3/004 ,  B81B2201/045 ,  B81B2203/058 ,  B81C2201/053 ,  G02B6/3514 ,  G02B6/3546 ,  G02B6/3566 ,  G02B6/357 ,  G02B6/3572 ,  G02B6/358

Abstract: A microelectromechanical systems (MEMS) element, MEMS optical switch and MEMS fabrication method are described. The MEMS element comprises a crystalline and moveable element is moveably attached to the substrate. The moveable element includes a perpendicular portion oriented substantially perpendicular to a plane of the substrate. The crystal structure of the perpendicular portion and substrate are substantially similar. The moveable element moveable is moveably attached to the substrate for motion substantially constrained to a plane oriented substantially perpendicular to a plane of the substrate. In at least one position, a part of a perpendicular portion of the moveable element projects beyond a surface of the substrate. The moveable element may be retained in place by a latch. The perpendicular portion may be formed substantially perpendicular portion to the substrate. An array of such structures can be implemented to work as an optical switch. The optical switch may comprise a crystalline substrate and one or more moveable elements moveably attached to the substrate. The MEMS elements may be fabricated by providing a substrate; forming one or more trenches in the substrate to define a perpendicular portion of a element; and moveably attaching the moveable element to a first surface of the substrate; removing a portion of the substrate such that at least a part of the perpendicular portion projects beyond a second surface of the substrate. The various embodiments provide for a robust and reliable MEMS elements that may be simply fabricated and densely packed.

Abstract translation: 描述了微机电系统（MEMS）元件，MEMS光开关和MEMS制造方法。 MEMS元件包括可移动地附接到基底的结晶和可移动元件。 可移动元件包括垂直于基本垂直于基底平面的垂直部分。 垂直部分和基底的晶体结构基本相似。 可移动的可移动元件可移动地附接到基板，用于基本上约束到基本上垂直于基板的平面定向的平面的运动。 在至少一个位置中，可移动元件的垂直部分的一部分突出超过衬底的表面。 可移动元件可以通过闩锁保持在适当的位置。 垂直部分可以形成为基本上垂直于基底的部分。 可以实现这种结构的阵列以用作光学开关。 光学开关可以包括结晶衬底和可移动地附接到衬底的一个或多个可移动元件。 可以通过提供衬底来制造MEMS元件; 在所述衬底中形成一个或多个沟槽以限定元件的垂直部分; 以及将所述可移动元件可移动地附接到所述基板的第一表面; 去除所述基底的一部分，使得所述垂直部分的至少一部分突出超过所述基底的第二表面。 各种实施例提供了可以简单地制造和密集包装的鲁棒且可靠的MEMS元件。

公开(公告)号：US06506620B1

公开(公告)日：2003-01-14

申请号：US09724515

申请日：2000-11-27

Applicant: Bruce R. Scharf ,  Joel A. Kubby ,  Chuang-Chia Lin ,  Alex T. Tran ,  Andrew J. Zosel ,  Peter M. Gulvin ,  Jingkuang Chen

Inventor： Bruce R. Scharf ,  Joel A. Kubby ,  Chuang-Chia Lin ,  Alex T. Tran ,  Andrew J. Zosel ,  Peter M. Gulvin ,  Jingkuang Chen

IPC: H01L2100

CPC classification number: B81C1/00484 ,  B81B2201/042 ,  B81B2203/0118 ,  B81C1/00666 ,  B81C2201/0142

Abstract: The present invention provides a micromechanical or microoptomechanical structure produced by a process comprising defining the structure in a single-crystal silicon layer separated by an insulator layer from a substrate layer; selectively etching the single crystal silicon layer; depositing and etching a polysilicon layer on the insulator layer, with remaining polysilicon forming mechanical elements of the structure; metalizing a backside of the structure; and releasing the formed structure.

Abstract translation: 本发明提供了一种微机械或微机电结构，其通过包括限定由绝缘体层与衬底层分隔的单晶硅层中的结构的方法而产生; 选择性地蚀刻单晶硅层; 沉积和蚀刻绝缘体层上的多晶硅层，剩余的多晶硅形成结构的机械元件; 金属化结构的背面; 并释放形成的结构。

公开(公告)号：US06479311B1

公开(公告)日：2002-11-12

申请号：US09724506

申请日：2000-11-27

Applicant: Bruce R. Scharf ,  Joel A. Kubby ,  Jingkuang Chen ,  Peter M. Gulvin ,  Chuang-Chia Lin ,  Alex T. Tran

Inventor： Bruce R. Scharf ,  Joel A. Kubby ,  Jingkuang Chen ,  Peter M. Gulvin ,  Chuang-Chia Lin ,  Alex T. Tran

IPC: H01L2100

CPC classification number: B81C1/00666 ,  B81B2201/047 ,  B81B2203/0118

Abstract: The present invention provides a micromechanical or microoptomechanical structure. The structure is produced by a process comprising defining a pattern on a single crystal silicon layer separated by an insulator layer from a substrate layer; defining a structure in the single-crystal silicon layer; depositing and etching a polysilicon layer on the single crystal silicon layer, with remaining polysilcon forming mechanical or optical elements of the structure; and releasing the formed structure.

Abstract translation: 本发明提供一种微机械或微机电结构。 该结构通过一种工艺制造，该方法包括在由绝缘体层与衬底层隔开的单晶硅层上限定图案; 限定单晶硅层中的结构; 沉积和蚀刻单晶硅层上的多晶硅层，其余的聚硅氧烷形成该结构的机械或光学元件; 并释放形成的结构。

公开(公告)号：US6166467A

公开(公告)日：2000-12-26

申请号：US209040

申请日：1998-12-10

Applicant: Wei-Shin Tsai ,  Chia-Lin Wang

Inventor： Wei-Shin Tsai ,  Chia-Lin Wang

IPC: H02K1/18 ,  H02K5/04 ,  H02K5/00

CPC classification number: H02K5/04 ,  H02K1/185

Abstract: An improved motor housing with a slop structure at one side of the housing, the slot structure is arranged with ledges along its outer edges in which several threaded holes are provided for placing bolts through which clamping level of the outer body can be controlled so that a stator core can be inserted or removed easily and repeatedly, resulting in low cost, simplified assembling process, and facilitating modification and test of a motor in the development stage in research institutions.

Abstract translation: 一种改进的电机壳体，其在壳体的一侧具有倾斜结构，槽结构沿着其外边缘布置有凸缘，其中设置有多个螺纹孔用于放置螺栓，通过该螺栓可以控制外部主体的夹紧水平，使得 定子芯可以方便，反复地插入或取出，从而降低了成本，简化了组装过程，并促进了研究机构开发阶段电机的修改和测试。

公开(公告)号：US5967049A

公开(公告)日：1999-10-19

申请号：US997288

申请日：1997-12-23

Applicant: John C. Seymour ,  Chia-Lin Chu

Inventor： John C. Seymour ,  Chia-Lin Chu

IPC: B41F31/02 ,  B41F31/00 ,  B41F31/04 ,  B41F31/14

CPC classification number: B41F31/045 ,  B41F31/00

Abstract: A method is disclosed for correction of the effects of ink back-flow and lateral flow in the inking system of a web-offset printing press. A plate coverage equation dependent on plate coverage is used to compensate for ink back-flow into the ink reservoir. An ink key distribution function is utilized to correct for the blurring effects of lateral ink spread caused by the action of vibrator rollers. A correction is also made for the ink saturation effect. The method is applicable to an ink key preset system.

Abstract translation: 公开了一种用于校正卷筒纸胶版印刷机的上墨系统中墨回流和侧向流动的影响的方法。 使用取决于板覆盖度的板覆盖方程来补偿油墨回流到油墨储存器中。 使用墨水键分布功能来校正由振动器辊的作用引起的侧向墨水扩散的模糊效果。 还对墨饱和效果进行了修正。 该方法适用于墨水键预设系统。