公开(公告)号：US20070128777A1

公开(公告)日：2007-06-07

申请号：US11561572

申请日：2006-11-20

Applicant: Huaxiang YIN ,  Takashi NOGUCHI ,  Hyuk LIM ,  Wenxu XIANYU ,  Hans CHO

Inventor： Huaxiang YIN ,  Takashi NOGUCHI ,  Hyuk LIM ,  Wenxu XIANYU ,  Hans CHO

IPC: H01L21/84 ,  H01L27/12

CPC classification number: H01L27/12 ,  H01L29/78609 ,  H01L29/78696

Abstract: A thin film transistor comprises an Si-based channel having a nonlinear electron-moving path, a source and a drain disposed at both sides of the channel, a gate disposed above the channel, an insulator interposed between the channel and the gate, and a substrate supporting the channel and the source and the drain disposed at either side of the channel respectively.

Abstract translation: 薄膜晶体管包括具有非线性电子移动路径的Si基通道，设置在沟道两侧的源极和漏极，设置在沟道上方的栅极，介于通道和栅极之间的绝缘体，以及 支撑通道的基板，分别设置在通道的两侧的源极和漏极。

公开(公告)号：US20060144323A1

公开(公告)日：2006-07-06

申请号：US11311228

申请日：2005-12-20

Applicant: Wenxu Xianyu ,  Takashi Noguchi ,  Young-soo Park ,  Hans Cho ,  Huaxiang Yin

Inventor： Wenxu Xianyu ,  Takashi Noguchi ,  Young-soo Park ,  Hans Cho ,  Huaxiang Yin

IPC: C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: H01L21/26506 ,  H01L21/268 ,  H01L21/32134 ,  H01L21/76254 ,  H01L21/76256 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/66772

Abstract: A method of fabricating a large substrate with a locally integrated single crystalline silicon layer is provided. The method includes: forming a buffer layer on a support plate; separately fabricating a single crystalline silicon layer; attaching the single crystalline silicon layer having a predetermined thickness, which is separately fabricated, to a predetermined portion in the support plate; forming a non-single crystalline silicon layer having a predetermined thickness to cover the single crystalline silicon layer and the buffer layer; and processing the non-single crystalline silicon layer to expose a surface of the non-single crystalline silicon layer and to level the surface of the non-single crystalline silicon layer with a surface of the amorphous silicon layer.

公开(公告)号：US20060134894A1

公开(公告)日：2006-06-22

申请号：US11283874

申请日：2005-11-22

Applicant: Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Kyung-bae Park

Inventor： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Kyung-bae Park

IPC: H01L21/84 ,  H01L21/20

CPC classification number: H01L21/02675 ,  H01L21/2026 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/12 ,  H01L27/1281

Abstract: A method of manufacturing a polycrystalline Si film and a method of manufacturing a stacked transistor are provided. The method of manufacturing the polycrystalline Si film includes preparing an insulating substrate on which is formed a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, sequentially formed, forming an interconnection metal line separated from the gate, forming an insulating layer that covers the transistor and the interconnection metal line, forming an amorphous silicon layer on the insulating layer; and annealing the amorphous silicon layer.

Abstract translation: 提供一种制造多晶Si膜的方法和制造堆叠晶体管的方法。 制造多晶Si膜的方法包括制备绝缘基板，其上形成有依次形成的多晶硅，具有多晶硅有源层，栅极绝缘层和栅极，形成与栅极分离的互连金属线， 形成覆盖晶体管和互连金属线的绝缘层，在绝缘层上形成非晶硅层; 并退火非晶硅层。

公开(公告)号：US20060068507A1

公开(公告)日：2006-03-30

申请号：US11233363

申请日：2005-09-23

Applicant: Wenxu Xianyu ,  Takashi Noguchi ,  Hans Cho ,  Jang-Yeon Kwon ,  Huaxiang Yin

Inventor： Wenxu Xianyu ,  Takashi Noguchi ,  Hans Cho ,  Jang-Yeon Kwon ,  Huaxiang Yin

IPC: H01L21/00 ,  H01L21/8242

CPC classification number: H01L21/02356 ,  H01L21/02197 ,  H01L21/31691 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/12

Abstract: A method of forming a material (e.g., ferroelectric) film, a method of manufacturing a capacitor, and a method of forming a semiconductor memory device using the method of forming the (e.g., ferroelectric) film are provided. Pursuant to an example embodiment of the present invention, a method of forming a ferroelectric film includes preparing a substrate, depositing an amorphous ferroelectric film on the substrate, and crystallizing the amorphous ferroelectric film by irradiating it with a laser beam. According to still another example embodiment of the present invention, a method of forming a ferroelectric film may reduce the thermal damage to other elements because the ferroelectric film may be formed at a temperature lower than about 500° C. to about 550°C.

Abstract translation: 提供了形成材料（例如铁电体）膜的方法，制造电容器的方法，以及使用形成（例如铁电体）膜的方法形成半导体存储器件的方法。 根据本发明的示例性实施例，形成铁电体膜的方法包括制备基板，在基板上沉积非晶铁电体膜，并通过用激光束照射非晶强电介质膜使其结晶。 根据本发明的另一示例性实施例，形成铁电体膜的方法可以减少对其它元件的热损伤，因为铁电体膜可以在低于约500℃至约550℃的温度下形成。

公开(公告)号：US20050145843A1

公开(公告)日：2005-07-07

申请号：US11013398

申请日：2004-12-17

Applicant: Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim

Inventor： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04 ,  H01L21/00

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/7855

Abstract: A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a substrate; a buffer layer formed on the substrate; a source and a drain spaced apart from each other on the buffer layer; a channel layer formed on the buffer layer to connect the source and the drain with each other; and a gate formed on the buffer layer to be spaced apart from the source, the drain and the channel layer.

Abstract translation: 提供薄膜晶体管及其制造方法。 薄膜晶体管包括基板; 形成在所述基板上的缓冲层; 在缓冲层上彼此间隔开的源极和漏极; 形成在所述缓冲层上的沟道层，以将所述源极和所述漏极彼此连接; 以及形成在缓冲层上以与源极，漏极和沟道层间隔开的栅极。

公开(公告)号：US10068990B2

公开(公告)日：2018-09-04

申请号：US14387830

申请日：2013-08-06

Applicant: Huaxiang Yin ,  Xiaolong Ma ,  Weijia Xu ,  Qiuxia Xu ,  Huilong Zhu

Inventor： Huaxiang Yin ,  Xiaolong Ma ,  Weijia Xu ,  Qiuxia Xu ,  Huilong Zhu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423

Abstract: A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

公开(公告)号：US09312187B2

公开(公告)日：2016-04-12

申请号：US13520791

申请日：2012-04-11

Applicant: Huaxiang Yin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

Abstract: The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.

Abstract translation: 本发明公开了一种半导体器件，包括第一MOSFET; 第二个MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力衬垫; 覆盖所述第二MOSFET并具有第二应力的第二应力衬垫; 其中所述第二应力衬垫和/或所述第一应力衬垫包括金属氧化物。 根据本发明的高应力CMOS及其制造方法，通过使用CMOS兼容工艺，分别在PMOS和NMOS上选择性地形成包含金属氧化物的应力层，由此，沟道区域的载流子迁移率有效地 增强了设备的性能，提高了设备​​性能。

公开(公告)号：US20150179797A1

公开(公告)日：2015-06-25

申请号：US14355664

申请日：2012-07-03

Applicant: Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66636 ,  H01L29/7834

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

Abstract translation: 本发明公开了一种半导体器件，其包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构下的衬底中的沟道区，以及沟道区两侧的源极和漏极区，其中存在 在形成源极和漏极区的沟道区的下侧和两侧具有应力层。 根据本发明的半导体器件及其制造方法，在由硅系材料制成的沟道区域的两侧和下方形成应力层，以作用于沟道区域，从而有效地增加 通道区域的载波移动性和设备性能的提高。

公开(公告)号：US20150115374A1

公开(公告)日：2015-04-30

申请号：US14387143

申请日：2012-04-26

Applicant: Huaxiang Yin ,  Xiaolong Ma ,  Changliang Qi ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Xiaolong Ma ,  Changliang Qi ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66575 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

Abstract: The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.

Abstract translation: 本发明提供一种包括基板的半导体结构; 衬底上的栅极堆叠; 在栅极堆叠的侧壁上的间隔物; 通过外延生长形成在栅极堆叠的两侧的衬底中的源极/漏极结延伸; 以及在源极/漏极结延伸部的两侧上的衬底中的源极/漏极区域。 因此，本发明还提供了制造半导体结构的方法。 本发明可以提供具有高掺杂浓度和低结深度的源极/漏极结延伸，从而有效地改善了半导体结构的性能。

公开(公告)号：US09006057B2

公开(公告)日：2015-04-14

申请号：US13989164

申请日：2012-07-31

Applicant: Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

Inventor： Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

IPC: H01L21/36 ,  H01L27/088 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/265

CPC classification number: H01L21/30604 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form Σ-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the Σ-shaped source/drain grooves.

Abstract translation: 公开了制造半导体器件的方法。 在一个实施例中，该方法包括：在衬底上形成栅叠层; 在栅极堆叠的两侧蚀刻衬底以形成C形源极/漏极沟槽; 并对C形源极/漏极沟槽进行湿式蚀刻以形成S形的源极/漏极沟槽。 通过该方法，能够有效地增加施加于沟道区域的应力，精确地控制源极/漏极沟槽的深度，并且可以减小沟槽的侧壁和底部的粗糙度，从而通过蚀刻C来减少缺陷 形状的源极/漏极沟槽，然后进一步湿法蚀刻它们以形成源极/漏极沟槽。