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    Allocation of Shared Reserve Memory to Queues in a Network Device
    112.
    发明公开
    Allocation of Shared Reserve Memory to Queues in a Network Device 审中-公开

    公开(公告)号：US20230283575A1

    公开(公告)日：2023-09-07

    申请号：US17588385

    申请日：2022-01-31

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Niv Aibester ,  Barak Gafni

    IPC: H04L49/103 ,  H04L49/9005 ,  H04L49/9047 ,  H04L45/122 ,  H04L47/30

    CPC classification number: H04L49/103 ,  H04L45/122 ,  H04L47/30 ,  H04L49/9005 ,  H04L49/9047

    Abstract: A network device includes one or more ports, a packet processor, and a memory management circuit. The one or more ports are to communicate packets over a network. The packet processor is to process the packets using a plurality of queues. The memory management circuit is to maintain a shared buffer in a memory and adaptively allocate memory resources from the shared buffer to the queues, to maintain in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by a defined subset of the queues, to identify in the subset a queue that (i) requires additional memory resources, (ii) is not eligible for additional allocation from the shared buffer, and (iii) meets an eligibility condition for the shared-reserve memory pool, and to allocate memory resources to the identified queue from the shared-reserve memory pool.

    Efficient Memory Utilization for Cartesian Products of Rules
    113.
    发明公开
    Efficient Memory Utilization for Cartesian Products of Rules 审中-公开

    公开(公告)号：US20230269310A1

    公开(公告)日：2023-08-24

    申请号：US17679160

    申请日：2022-02-24

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Gil Levy ,  Aviv Kfir

    IPC: H04L69/22 ,  H04L45/745 ,  H04L45/74 ,  H03M7/30

    CPC classification number: H04L69/22 ,  H04L45/7457 ,  H04L45/742 ,  H03M7/3082

    Abstract: A network device includes one or more ports, and action-select circuitry. The ports are to exchange packets over a network. The act-ion-select circuitry is to determine, for a given packet, a first search key based on a first header field of the given packet, and a second search key based on a second header field of the given packet, to compare the first search key to a first group of compare values, to output a multi-element vector responsively to a match between the first search key and a first compare value, to generate a composite search key by concatenating the second search key and the multi-element vector, to compare the composite search key to a second group of compare values, and, responsively to a match between the composite search key and a second compare value, to output an action indicator for applying to the given packet.

    MALICIOUS ACTIVITY DETECTION IN MEMORY OF A DATA PROCESSING UNIT USING MACHINE LEARNING DETECTION MODELS
    115.
    发明公开
    MALICIOUS ACTIVITY DETECTION IN MEMORY OF A DATA PROCESSING UNIT USING MACHINE LEARNING DETECTION MODELS 审中-公开

    公开(公告)号：US20230259614A1

    公开(公告)日：2023-08-17

    申请号：US17864306

    申请日：2022-07-13

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Vadim Gechman ,  Nir Rosen ,  Haim Elisha ,  Bartley Richardson ,  Rachel Allen ,  Ahmad Saleh ,  Rami Ailabouni ,  Thanh Nguyen

    IPC: G06F21/55

    CPC classification number: G06F21/552 ,  G06F2221/034

    Abstract: Apparatuses, systems, and techniques for detecting that one or more computer programs executed by a host device are subject to malicious activity using a machine learning (ML) detection system. An integrated circuit is coupled to physical memory of a host device via a host interface. The integrated circuit hosts a hardware-accelerated security service to protect one or more computer programs executed by the host device. The security service extracts a set of features from data stored in the physical memory, the data being associated with the one or more computer programs. The security service determines, using the ML detection system, whether the one or more computer programs are subject to malicious activity based on the set of features. The security service outputs an indication of the malicious activity responsive to a determination that the one or more computer programs are subject to the malicious activity.

    METHODS AND SYSTEMS FOR INTER-STACK COMMUNICATION FOR LOGICAL VOLUME MANAGEMENT
    118.
    发明公开
    METHODS AND SYSTEMS FOR INTER-STACK COMMUNICATION FOR LOGICAL VOLUME MANAGEMENT 审中-公开

    公开(公告)号：US20230236769A1

    公开(公告)日：2023-07-27

    申请号：US17586417

    申请日：2022-01-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Omri Kahalon ,  Gal Shalom ,  Aviad Yehezkel ,  Liran Liss ,  Oren Duer ,  Rabie Loulou ,  Maxim Gurtovoy

    IPC: G06F3/06

    CPC classification number: G06F3/0689 ,  G06F3/067 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0613

    Abstract: Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.

    Accurate time-stamping of outbound packets
    119.
    发明授权
    Accurate time-stamping of outbound packets 有权

    公开(公告)号：US11711158B2

    公开(公告)日：2023-07-25

    申请号：US17359667

    申请日：2021-06-28

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Hillel Chapman ,  Roi Geuli ,  Eyal Serbro

    IPC: H04J3/06

    CPC classification number: H04J3/0661 ,  H04J3/062

    Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.

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