公开(公告)号：US07655949B2

公开(公告)日：2010-02-02

申请号：US11859203

申请日：2007-09-21

Applicant: Sung-hoon Yang ,  So-woon Kim ,  Tae-hyung Hwang ,  Yeon-joo Kim ,  Soo-wan Yoon ,  Chong-chul Chai

Inventor： Sung-hoon Yang ,  So-woon Kim ,  Tae-hyung Hwang ,  Yeon-joo Kim ,  Soo-wan Yoon ,  Chong-chul Chai

IPC: H01L27/14

CPC classification number: H01L27/283 ,  H01L27/285 ,  H01L27/3262

Abstract: A thin film transistors (TFTs) substrate is structured to maintain as constant across the area of the substrate a kickback voltage due to Miller capacitance between the drain and gate of each TFT even in the presence of manufacturing induced misalignments between the drain electrodes and corresponding gate lines. Each thin film transistor includes a gate electrode, an active layer formed on the gate electrode so as to overlap the gate electrode, first and second source electrodes respectively connected to first and second data lines each of which crosses the gate line while being insulated from the gate line, and an elongated drain electrode located between the first and second source electrodes and disposed over the gate electrode so as to a crossing length of the drain electrode is larger than an underlying width of the gate electrode such that misalignment induced shifts of the position of the gate electrode relative to the drain electrode does not substantially change overlap area between the two.

Abstract translation: 薄膜晶体管（TFT）衬底被构造成即使在漏电极和对应的栅极之间的制造引起的不对准的情况下，由于每个TFT的漏极和栅极之间的米勒电容也会在衬底的面积上保持一定的反冲电压 线条。 每个薄膜晶体管包括栅电极，形成在栅电极上以与栅电极重叠的有源层，分别连接到第一和第二数据线的第一和第二源电极，每个第一和第二数据线与栅极线交叉，同时与 栅极线和位于第一和第二源电极之间并设置在栅电极之上的细长漏极，以使漏电极的交叉长度大于栅电极的下伏宽度，使得未对准引起位置移动 相对于漏电极的栅极电极基本上不改变两者之间的重叠面积。

公开(公告)号：US20100019996A1

公开(公告)日：2010-01-28

申请号：US12486542

申请日：2009-06-17

Applicant: Chun-Gi YOU ,  Kap-Soo YOON ,  Gug-Rae JO ,  Sung-Hoon YANG ,  Ki-Hun JEONG ,  Seung-Hwan SHIM ,  Jae-Ho CHOI

Inventor： Chun-Gi YOU ,  Kap-Soo YOON ,  Gug-Rae JO ,  Sung-Hoon YANG ,  Ki-Hun JEONG ,  Seung-Hwan SHIM ,  Jae-Ho CHOI

IPC: G09G3/30 ,  H01L21/00

CPC classification number: H01L27/1251 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/7869

Abstract: A display substrate includes a switching transistor electrically connected to a gate line and a data line, the data line extending in a first direction substantially perpendicular to the gate line extending in a second direction, the switching transistor including a switching active pattern comprising amorphous silicon, a driving transistor electrically connected to a driving voltage line and the switching transistor, the driving voltage line extended in the first direction, the driving transistor including a driving active pattern comprising a metal oxide; and a light-emitting element electrically connected to the driving transistor.

Abstract translation: 显示基板包括电连接到栅极线和数据线的开关晶体管，所述数据线在基本上垂直于在第二方向延伸的栅极线的第一方向上延伸，所述开关晶体管包括包含非晶硅的开关有源图案， 电连接到驱动电压线的驱动晶体管和所述开关晶体管，所述驱动电压线在所述第一方向上延伸，所述驱动晶体管包括包含金属氧化物的驱动有源图案; 以及电连接到驱动晶体管的发光元件。

公开(公告)号：US20090098673A1

公开(公告)日：2009-04-16

申请号：US12334241

申请日：2008-12-12

Applicant: Sung-Hoon Yang ,  Kunal Satyabhushan Girotra ,  Byoung-June Kim

Inventor： Sung-Hoon Yang ,  Kunal Satyabhushan Girotra ,  Byoung-June Kim

IPC: H01L21/77

CPC classification number: H01L29/458 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/4908

Abstract: A TFT array panel-including a substrate, a gate line having a gate electrode, a gate insulating layer formed on the gate line, a data line having a source electrode and a drain electrode spaced apart from the source electrode, a passivation layer formed on the data line and the drain electrode, and a pixel electrode connected to the drain electrode is provided. The TFT array panel further includes a protection layer including Si under at least one of the gate insulating layer and the passivation layer to enhance reliability.

Abstract translation: 一种TFT阵列面板，包括基板，具有栅极电极的栅极线，栅极线上形成的栅极绝缘层，具有与源极间隔开的源极和漏电极的数据线，形成在源电极上的钝化层 提供数据线和漏电极以及连接到漏电极的像素电极。 TFT阵列板还包括在栅极绝缘层和钝化层中的至少一个之下包括Si的保护层，以增强可靠性。

公开(公告)号：US20080137016A1

公开(公告)日：2008-06-12

申请号：US11951175

申请日：2007-12-05

Applicant: So Woon KIM ,  Sung Hoon Yang ,  Chong Chul Chai

Inventor： So Woon KIM ,  Sung Hoon Yang ,  Chong Chul Chai

IPC: G02F1/1343 ,  H03K19/0175

CPC classification number: G02F1/13452

Abstract: A fanout line structure and a liquid crystal display panel and a liquid crystal display including the fanout line structure are presented. The fanout line structure connects a signal line to a bonding pad, and includes a plurality of fanout lines that are positioned apart from each other. The plurality of fanout lines are formed to have different lengths, and a hole pattern is formed in at least one of the plurality of fanout lines to reduce the difference in resistance levels between the fanout lines. The fanout structure significantly reduces any deterioration in image quality stemming from different resistance levels among the fanout lines.

Abstract translation: 提出了扇出线结构和液晶显示面板以及包括扇出线结构的液晶显示器。 扇出线结构将信号线连接到接合焊盘，并且包括彼此分开定位的多个扇出线。 多个扇出线形成为具有不同的长度，并且在多个扇出线中的至少一个中形成孔图案以减少扇出线之间的电阻水平差。 扇出结构显着降低了由扇出线之间的不同电阻水平引起的图像质量的任何劣化。

公开(公告)号：US20080123040A1

公开(公告)日：2008-05-29

申请号：US11985838

申请日：2007-11-16

Applicant: Sung-hoon Yang ,  So-woon Kim ,  Chong-chul Chai

Inventor： Sung-hoon Yang ,  So-woon Kim ,  Chong-chul Chai

IPC: G02F1/1345 ,  G02F1/13

CPC classification number: G02F1/136209 ,  G02F1/1345 ,  G02F2001/133388

Abstract: A liquid crystal display device includes a first substrate where a pixel thin film transistor is formed, a second substrate which is positioned opposite to the first substrate and a liquid crystal layer interposed between the first substrate and the second substrate. A light source is positioned beneath the first substrate, and joins the first substrate with the second substrate, the first substrate comprising: a first insulating substrate which has a display area where the pixel thin film transistor is formed and a non-display area which surrounds the display area; a gate line in the display area and the gate line being electrically connected to the pixel thin film transistor. A gate driving portion is formed in the non-display area to drive the gate line and comprises a driving thin film transistor; and a light blocking member which covers the gate driving part.

Abstract translation: 液晶显示装置包括形成有像素薄膜晶体管的第一基板，与第一基板相对的第二基板和介于第一基板和第二基板之间的液晶层。 光源位于第一衬底下方，并且将第一衬底与第二衬底接合，第一衬底包括：第一绝缘衬底，其具有形成像素薄膜晶体管的显示区域和围绕着像素薄膜晶体管的非显示区域 显示区; 显示区域中的栅极线和栅极线电连接到像素薄膜晶体管。 栅极驱动部分形成在非显示区域中以驱动栅极线并且包括驱动薄膜晶体管; 以及覆盖所述门驱动部的遮光部件。

公开(公告)号：US20080121890A1

公开(公告)日：2008-05-29

申请号：US11950476

申请日：2007-12-05

Applicant: Sung-Hoon YANG ,  Wan-Shick Hong ,  Kwan-Wook Jung

Inventor： Sung-Hoon YANG ,  Wan-Shick Hong ,  Kwan-Wook Jung

IPC: H01L29/786

CPC classification number: G02F1/136227 ,  C23C16/30 ,  G02F2001/136222 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3244 ,  H01L29/458 ,  H01L29/4908 ,  H01L51/56

Abstract: The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.

Abstract translation: 本发明涉及一种用于气相沉积低介电绝缘膜的方法，使用其的薄膜晶体管及其制备方法，更具体地涉及可以显着改善蒸气的低介电绝缘膜的气相沉积方法 同时保持低介电绝缘膜的性能，从而解决了寄生电容问题，以实现高开口率结构，并且通过使用硅烷气体通过CVD或PECVD方法蒸镀绝缘膜时可以减少处理时间，以形成 用于半导体器件的保护膜。 本发明还涉及使用该方法及其制备方法的薄膜晶体管。

公开(公告)号：US20080117373A1

公开(公告)日：2008-05-22

申请号：US11943400

申请日：2007-11-20

Applicant: Ji-Won SOHN ,  Jin-Won PARK ,  Seon-Ah CHO ,  Mee-Hye JUNG ,  Sung-Hoon YANG

Inventor： Ji-Won SOHN ,  Jin-Won PARK ,  Seon-Ah CHO ,  Mee-Hye JUNG ,  Sung-Hoon YANG

IPC: G02F1/1343

CPC classification number: G02F1/134309 ,  G02F2001/134318

Abstract: A panel assembly includes a gate wire, a data wire, a plurality of pixel electrodes, a liquid crystal layer, and a common electrode. The gate wire includes a plurality of gate lines and the data wire includes a plurality of data lines crossing and insulated from the gate lines. The pixel electrodes are insulated from each other and disposed on the data wire. The liquid crystal layer is disposed on the pixel electrodes and includes liquid crystal molecules, and a common electrode is disposed on the liquid crystal layer. The gate lines cross a center of the pixel electrodes, and the common electrode includes a plurality of cutting patterns that overlap the gate lines.

Abstract translation: 面板组件包括栅极线，数据线，多个像素电极，液晶层和公共电极。 栅极线包括多条栅极线，数据线包括与栅极线交叉并绝缘的多条数据线。 像素电极彼此绝缘并设置在数据线上。 液晶层设置在像素电极上并且包括液晶分子，并且公共电极设置在液晶层上。 栅极线穿过像素电极的中心，并且公共电极包括与栅极线重叠的多个切割图案。

公开(公告)号：US20070096097A1

公开(公告)日：2007-05-03

申请号：US11538394

申请日：2006-10-03

Applicant: Byoung-June Kim ,  Sung-Hoon Yang ,  Min-Seok Oh ,  Jae-HO Choi ,  Yong-Mo Choi

Inventor： Byoung-June Kim ,  Sung-Hoon Yang ,  Min-Seok Oh ,  Jae-HO Choi ,  Yong-Mo Choi

IPC: H01L29/04 ,  H01L21/84

CPC classification number: H01L29/78669 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/66765

Abstract: A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a predetermined distance. The buffer layer is formed between the active layer and the source and drain electrodes. The buffer layer has a substantially continuously varying content ratio corresponding to a buffer layer thickness. The buffer layer is formed to suppress oxidation of the active layer, and reduce contact resistance.

Abstract translation: TFT包括栅电极，有源层，源电极，漏电极和缓冲层。 栅电极形成在基板上; 在栅电极上形成有源层。 形成在有源层上的源电极和漏电极分开预定的距离。 缓冲层形成在有源层与源极和漏极之间。 缓冲层具有对应于缓冲层厚度的基本连续变化的含量比。 形成缓冲层以抑制有源层的氧化，并降低接触电阻。

公开(公告)号：US20060017862A1

公开(公告)日：2006-01-26

申请号：US10531829

申请日：2003-08-30

Applicant: Jean-Ho Song ,  Joon-Hoo Choi ,  Sung-Hoon Yang ,  Chong-Chul Chai

Inventor： Jean-Ho Song ,  Joon-Hoo Choi ,  Sung-Hoon Yang ,  Chong-Chul Chai

IPC: G02F1/136

CPC classification number: G06K9/0004 ,  G02F1/13338 ,  G02F2001/13312

Abstract: A liquid crystal display device having fingerprint identification device for enhancing aperture ratio and transmissivity of a TFT-LCD panel is disclosed. A fingerprint identification substrate (400) is attached to a TFT substrate (300). The TFI substrate has color-filter-on-array structure in which the color filters (336) and the thin film transistors can be eliminated, the aperture ratio is increased, and the quality of image display is enhanced. In addition, the transmissivity is increased according to the decrease of the number of glass substrate used in the liquid crystal display device, so that the sensitivity of fingerprint identification is enhanced.

Abstract translation: 公开了一种具有用于提高TFT-LCD面板的开口率和透射率的指纹识别装置的液晶显示装置。 指纹识别基板（400）附接到TFT基板（300）。 TFI基板具有彩色滤光器阵列结构，其中可以消除滤色器（336）和薄膜晶体管，孔径比增加，并且图像显示的质量得到提高。 此外，根据液晶显示装置中使用的玻璃基板的数量的减少，透射率增加，从而提高了指纹识别的灵敏度。

公开(公告)号：US09570621B2

公开(公告)日：2017-02-14

申请号：US12977853

申请日：2010-12-23

Applicant: Ki-Hun Jeong ,  Do-Hyun Kim ,  Dong-Hoon Lee ,  Kap-Soo Yoon ,  Jae-Ho Choi ,  Sung-Hoon Yang ,  Pil-Sang Yun ,  Seung-Mi Seo

Inventor： Ki-Hun Jeong ,  Do-Hyun Kim ,  Dong-Hoon Lee ,  Kap-Soo Yoon ,  Jae-Ho Choi ,  Sung-Hoon Yang ,  Pil-Sang Yun ,  Seung-Mi Seo

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78606 ,  H01L29/78633

Abstract: The present invention discloses a thin film transistor (TFT), a method for manufacturing the TFT, and a display substrate using the TFT that may prevent degradation of the characteristics of an oxide semiconductor contained in the TFT by blocking external light from entering a channel region of the oxide semiconductor. The TFT includes an oxide semiconductor layer; a protective layer overlapping a channel region of the oxide semiconductor layer; an opaque layer disposed between the oxide semiconductor layer and the protective layer; a source electrode contacting a first side of the oxide semiconductor layer; a drain electrode contacting a second side of the oxide semiconductor layer and facing the source electrode across the channel region; a gate electrode to apply an electric field to the oxide semiconductor layer; and a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer.

Abstract translation: 本发明公开了一种薄膜晶体管（TFT），TFT的制造方法以及使用该TFT的显示基板，其可以防止外部光阻挡进入沟道区域而使TFT中包含的氧化物半导体的特性劣化 的氧化物半导体。 TFT包括氧化物半导体层; 与所述氧化物半导体层的沟道区域重叠的保护层; 设置在所述氧化物半导体层和所述保护层之间的不透明层; 与氧化物半导体层的第一面接触的源电极; 漏电极，与所述氧化物半导体层的第二侧接触，并跨过所述沟道区面对所述源电极; 用于向氧化物半导体层施加电场的栅电极; 以及设置在栅电极和氧化物半导体层之间的栅极绝缘层。