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264 条记录 (耗时 0.021 秒)

    Asymmetric FinFET semiconductor devices and methods for fabricating the same
    113.
    发明授权
    Asymmetric FinFET semiconductor devices and methods for fabricating the same 有权
    非对称FinFET半导体器件及其制造方法

    公开(公告)号：US09583597B2

    公开(公告)日：2017-02-28

    申请号：US13902540

    申请日：2013-05-24

    申请人： GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

    发明人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66795 ,  H01L27/0886 ,  H01L29/785 ,  H01L29/7855

    摘要： Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first space between the fins structures and forming a first metal gate in the first space between the fin structures. A second portion of the conformal liner is removed, leaving a second space between the fin structures and forming a second metal gate in the second space between the fin structures.

    摘要翻译： 提供非对称FinFET器件及其制造方法。 在一个实施例中，一种方法包括提供包括形成在其上的多个翅片结构的半导体衬底，并且在翅片结构上沉积保形衬垫。 去除保形衬套的第一部分，在翅片结构之间留下第一空间，并在翅片结构之间的第一空间中形成第一金属浇口。 去除保形衬套的第二部分，在翅片结构之间留下第二空间，并在翅片结构之间的第二空间中形成第二金属浇口。

    Semiconductor devices with self-aligned contacts and low-k spacers
    115.
    发明授权
    Semiconductor devices with self-aligned contacts and low-k spacers 有权
    具有自对准触点和低k间隔物的半导体器件

    公开(公告)号：US09543426B2

    公开(公告)日：2017-01-10

    申请号：US13957587

    申请日：2013-08-02

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/768

    CPC分类号： H01L29/78 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

    摘要： One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

    摘要翻译： 本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分，从而暴露牺牲栅电极的侧壁的至少一部分，并在牺牲栅电极的暴露的侧壁上形成衬垫层。 在该示例中，该方法还包括在衬垫层之上形成牺牲间隙填充材料，暴露和去除牺牲栅极电极，从而限定由衬里层横向限定的栅极腔，形成替代栅极结构，去除牺牲层 间隙填充材料并形成邻近衬层的低k侧壁间隔物。 还公开了一种器件，其包括栅极覆盖层，位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层，以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。

    Field effect transistor device spacers
    116.
    发明授权
    Field effect transistor device spacers 有权
    场效应晶体管器件间隔物

    公开(公告)号：US09536981B1

    公开(公告)日：2017-01-03

    申请号：US14868414

    申请日：2015-09-29

    申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

    发明人： Xiuyu Cai ,  Sanjay C. Mehta ,  Tenko Yamashita

    IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L27/0924 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

    摘要： A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

    摘要翻译： 一种用于制造场效应晶体管器件的方法，包括在衬底上形成翅片，在鳍片上形成第一虚拟栅极堆叠和第二虚拟栅极堆叠，形成与鳍片相邻的间隔物，第一伪栅极堆叠和第二虚拟栅极 栅极堆叠，蚀刻以去除所述鳍片的部分并形成由所述间隔物部分地限定的第一空腔，在所述第一腔体中沉积绝缘体材料，在第一虚拟栅极堆叠和所述鳍片的部分上图案化掩模，蚀刻以去除暴露部分 并且在所述鳍的暴露部分上外延生长第一半导体材料。

    Methods of forming different FinFET devices having different fin heights and an integrated circuit product containing such devices
    117.
    发明授权
    Methods of forming different FinFET devices having different fin heights and an integrated circuit product containing such devices 有权
    形成具有不同翅片高度的不同FinFET器件的方法和包含这种器件的集成电路产品

    公开(公告)号：US09530775B2

    公开(公告)日：2016-12-27

    申请号：US13916013

    申请日：2013-06-12

    申请人： GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    发明人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/66795 ,  H01L29/7851

    摘要： One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height.

    摘要翻译： 本文公开的一种说明性方法包括在衬底的多个有源区域中形成多个沟槽，所述多个有源区域分别限定用于第一和第二FinFET器件的至少第一多个鳍片和第二多个鳍片，以形成邻近 第一和第二多个翅片，其中与第一鳍片和第二鳍片相邻的衬垫材料具有不同的厚度。 该方法还包括去除绝缘材料以暴露衬里材料的部分，执行蚀刻工艺以去除衬里材料的部分，以便将第一组多个鳍中的至少一个翅片暴露于第一高度，并且将至少一个 第二多个翅片到与第一高度不同的第二高度。

    DUAL CHANNEL FINFET WITH RELAXED PFET REGION
    118.
    发明申请
    DUAL CHANNEL FINFET WITH RELAXED PFET REGION 有权
    具有松弛PFET区域的双通道FINFET

    公开(公告)号：US20160284607A1

    公开(公告)日：2016-09-29

    申请号：US14670800

    申请日：2015-03-27

    申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

    发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

    IPC分类号： H01L21/84 ,  H01L29/78 ,  H01L27/12

    CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/7849

    摘要： Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

    摘要翻译： 制造半导体器件包括提供设置在电介质层上的应变半导体材料（SSM）层，在SSOI结构上形成第一多个鳍片，第一组多个鳍片中的至少一个鳍片在nFET区域中，并且至少一个 鳍状物在pFET区域中，在pFET区域中的至少一个鳍片的SSM层的部分之下蚀刻介电层的部分，通过蚀刻清除的填充区域，从至少一个鳍片形成第二多个鳍片 所述nFET区域使得每个鳍片包括设置在所述电介质层上的所述SSM层的一部分，以及从所述pFET区域中的所述至少一个翅片形成第三多个翅片，使得每个翅片包括设置在所述SSM层上的部分 可流动的氧化物。

    MACRO TO MONITOR N-P BUMP
    119.
    发明申请
    MACRO TO MONITOR N-P BUMP 有权
    宏观监控N-P BUMP

    公开(公告)号：US20160284602A1

    公开(公告)日：2016-09-29

    申请号：US14669055

    申请日：2015-03-26

    申请人： International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

    发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

    IPC分类号： H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L21/66 ,  H01L21/768

    CPC分类号： H01L21/823871 ,  H01L21/30625 ,  H01L21/3085 ,  H01L21/82385 ,  H01L22/12 ,  H01L22/30

    摘要： A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a fabrication process. The macro is a test layout of a semiconductor structure having n-p bumps at junctions between NFET areas and PFET areas. Optical critical dimension (OCD) spectroscopy is performed to obtain the measurements of the n-p bumps on the macro. An amount of chemical mechanical polishing is determined to remove the n-p bumps on the macro based on the measurements of the n-p bumps on the macro. Chemical mechanical polishing is performed to remove the n-p bumps on the macro. The amount previously determined for the macro is utilized to perform chemical mechanical polishing for each of the dual spacer, dual epitaxial layer transistor devices having been fabricated under the fabrication process of the macro in which the fabrication process produced the n-p bumps.

    摘要翻译： 技术涉及制造用于双间隔物，双外延晶体管器件中的测量的宏。 宏是根据制造工艺制造的。 该宏是在NFET区域和PFET区域之间的结处具有n-p个凸起的半导体结构的测试布局。 执行光临界尺度（OCD）光谱以获得宏观上的n-p凸块的测量。 基于宏观上的n-p凸块的测量，确定了一定量的化学机械抛光以去除宏观上的n-p凸块。 进行化学机械抛光以除去宏观上的n-p凸块。 先前为宏确定的量用于对在制造工艺产生n-p个凸块的宏的制造过程中制造的每个双间隔物，双外延层晶体管器件进行化学机械抛光。