公开(公告)号：US20130062668A1

公开(公告)日：2013-03-14

申请号：US13672040

申请日：2012-11-08

Applicant: International Business Machines Corporation

Inventor： Erik M. Dahlstrom ,  Peter B. Gray ,  Qizhi Liu

IPC: H01L29/737 ,  G06F17/50

CPC classification number: H01L29/7378 ,  H01L29/66242

Abstract: Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.

Abstract translation: 具有降低的基极电阻的异质结双极晶体管，以及用于BiCMOS集成电路的异质结双极晶体管和设计结构的制造方法。 异质结双极晶体管包括在本征基极和外部基极之间的导电层。 导电层由诸如硅化物的导电材料构成，其电阻率低于形成本征碱和非本征基的材料。

公开(公告)号：US09917005B2

公开(公告)日：2018-03-13

申请号：US15437736

申请日：2017-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L21/306 ,  H01L29/06

CPC classification number: H01L21/76289 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

公开(公告)号：US09837514B2

公开(公告)日：2017-12-05

申请号：US15073763

申请日：2016-03-18

Applicant: International Business Machines Corporation

Inventor： Joseph R. Greco ,  Qizhi Liu ,  Aaron L. Vallett ,  Robert F. Vatter

IPC: H01L29/73 ,  H01L29/732 ,  H01L29/66 ,  H01L29/10 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423 ,  H01L29/45 ,  H01L27/082 ,  H01L27/06 ,  H01L29/417 ,  H01L21/8249

CPC classification number: H01L29/732 ,  H01L21/76232 ,  H01L21/76879 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/66287

Abstract: Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

公开(公告)号：US09818688B2

公开(公告)日：2017-11-14

申请号：US14945854

申请日：2015-11-19

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/522 ,  H01L23/66 ,  H01L49/02 ,  H01L29/06 ,  H01L21/762 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L29/16

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

公开(公告)号：US09666475B2

公开(公告)日：2017-05-30

申请号：US15083793

申请日：2016-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/266 ,  H01L21/764 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/76289 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

公开(公告)号：US09646993B2

公开(公告)日：2017-05-09

申请号：US14834696

申请日：2015-08-25

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  James S. Dunn ,  Blaine J. Gross ,  Qizhi Liu ,  James A. Slinkman

IPC: H01L21/70 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/165 ,  H01L29/45 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L27/1203 ,  H01L21/3081 ,  H01L21/764 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7842

Abstract: Various embodiments include field effect transistors (FETs) and related integrated circuit (IC) layouts. One FET includes: a silicon substrate including a set of trenches; a first oxide abutting the silicon substrate; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions; a gate structure overlying the second oxide between adjacent salicide regions; and a first contact contacting the gate structure; a second contact contacting one of the salicide regions; a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and an air gap in each of the set of trenches, the air gap surrounded by the third oxide.

公开(公告)号：US20160380055A1

公开(公告)日：2016-12-29

申请号：US14749836

申请日：2015-06-25

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu

IPC: H01L29/10 ,  H01L21/324 ,  H01L29/08 ,  H01L21/225 ,  H01L29/73 ,  H01L29/66

CPC classification number: H01L29/1004 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0821 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7371

Abstract: Device structure and fabrication methods for a bipolar junction transistor. A base layer is formed and an emitter is formed on a first portion of the base layer. A dopant-containing layer is deposited on a second portion of the base layer. Dopant is transferred from the dopant-containing layer into the second portion of the base layer to define an extrinsic base of the device structure.

Abstract translation: 双极结型晶体管的器件结构和制造方法。 形成基底层，并且在基底层的第一部分上形成发射体。 含有掺杂剂的层沉积在基层的第二部分上。 掺杂剂从含掺杂剂的层转移到基层的第二部分中以限定器件结构的外在基极。

公开(公告)号：US09337078B2

公开(公告)日：2016-05-10

申请号：US14024075

申请日：2013-09-11

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Qizhi Liu ,  Zhenzhen Ye ,  Yan Zhang

IPC: H01L21/762 ,  H01L23/367

CPC classification number: H01L21/76224 ,  H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to a structure herein, a silicon substrate has an active device in the silicon substrate. A dielectric film is on the active device. An isolation trench is in the dielectric film surrounding the active device. The trench extends through the dielectric film and at least partially into the silicon substrate. A core is in the isolation trench. The core comprises material having thermal conductivity greater than silicon dioxide and electrical conductivity approximately equal to silicon dioxide.

Abstract translation: 根据本文的结构，硅衬底在硅衬底中具有有源器件。 电介质膜位于有源器件上。 绝缘膜位于有源器件周围的绝缘膜中。 沟槽延伸穿过介电膜并至少部分地进入硅衬底。 核心在隔离槽。 核心包括具有大于二氧化硅的热导率和大致等于二氧化硅的导电性的材料。

公开(公告)号：US09323008B2

公开(公告)日：2016-04-26

申请号：US14224210

申请日：2014-03-25

Applicant: International Business Machines Corporation

Inventor： Zhong-Xiang He ,  Qizhi Liu ,  Ronald G. Meunier ,  Steven M. Shank

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/136 ,  G02B6/132

CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B2006/121 ,  G02B2006/12119

Abstract: Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.

Abstract translation: 公开了具有光波导的结构，该光波导具有第一级的第一段和在第一级和高级第二级之间延伸并且还沿第二级延伸的第二段。 具体地，波导包括在第一和第二介电层之间的第一段。 第二电介质层具有沟槽，该沟槽延伸到第一电介质层，并且其一侧位于与第一段的端部横向相邻的位置。 波导还包括从沟槽的底部在与第一部分相邻的一侧上延伸直到并沿着沟槽相对侧上的第二电介质层的顶表面延伸的第二部分。 第三介电层覆盖沟槽中的第二段和第二介电层的顶表面。 还公开了形成这种光电子结构的方法。

公开(公告)号：US20160071796A1

公开(公告)日：2016-03-10

申请号：US14945854

申请日：2015-11-19

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L29/16 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.