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    ISOLATION OF MIM FIN DRAM CAPACITOR
    111.
    发明申请
    ISOLATION OF MIM FIN DRAM CAPACITOR 审中-公开
    MIM FIN DRAM电容器的分离

    公开(公告)号：US20100258908A1

    公开(公告)日：2010-10-14

    申请号：US12822520

    申请日：2010-06-24

    申请人： BRIAN S. DOYLE ,  Dinesh Somasekhar ,  Robert S. Chau ,  Suman Datta

    发明人： BRIAN S. DOYLE ,  Dinesh Somasekhar ,  Robert S. Chau ,  Suman Datta

    IPC分类号： H01L29/92

    CPC分类号： H01L29/94 ,  H01L27/10852 ,  H01L28/40 ,  H01L29/785

    摘要： In one embodiment, a capacitor comprises a substrate, a first electrically insulating layer over the substrate, a fin comprising a semiconducting material over the first electrically insulating layer, a cap formed from a suicide material on the first semiconducting fin, a first electrically conducting layer over the first electrically insulating layer and adjacent to the fin, a second electrically insulating layer adjacent to the first electrically conducting layer and a second electrically conducting layer adjacent to the second electrically insulating

    摘要翻译： 在一个实施例中，电容器包括衬底，在衬底上的第一电绝缘层，在第一电绝缘层上的包括半导体材料的鳍，在第一半导体翅片上由硅化物材料形成的帽，第一导电层 在所述第一电绝缘层上并且与所述鳍相邻，与所述第一导电层相邻的第二电绝缘层和与所述第二电绝缘层相邻的第二导电层

    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
    117.
    发明授权
    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication 有权
    非平面半导体器件部分或完全缠绕在栅极电极和制造方法

    公开(公告)号：US07456476B2

    公开(公告)日：2008-11-25

    申请号：US10607769

    申请日：2003-06-27

    申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    IPC分类号： H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

    摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。