公开(公告)号：US07459360B2

公开(公告)日：2008-12-02

申请号：US11681454

申请日：2007-03-02

Applicant: James W. Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Jerome B. Lasky ,  Richard A. Phelps

Inventor： James W. Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Jerome B. Lasky ,  Richard A. Phelps

IPC: H01L21/8238

CPC classification number: H01L27/14689 ,  H01L27/14603 ,  H01L27/14609 ,  H01L31/0352

Abstract: A method of forming a pixel sensor cell structure. The method of forming the pixel cell comprises forming a doped layer adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.

Abstract translation: 一种形成像素传感器单元结构的方法。 形成像素单元的方法包括形成与传输栅极结构的第一侧相邻的掺杂层，用于耦合收集阱区和沟道区。 减少了由钉扎层引起的对电荷转移的电势障碍干扰。

公开(公告)号：US07361989B1

公开(公告)日：2008-04-22

申请号：US11528227

申请日：2006-09-26

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L23/48

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US07342268B2

公开(公告)日：2008-03-11

申请号：US10905277

申请日：2004-12-23

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

IPC: H01L31/062

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

Abstract: An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

Abstract translation: 一种图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光敏度的像素阵列。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：US20080042292A1

公开(公告)日：2008-02-21

申请号：US11465622

申请日：2006-08-18

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/3114 ,  H01L23/485 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L2224/05553 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

Abstract translation: 一种电子封装，其具有位于芯片上的至少一个接合焊盘，用于实现与集成电路的晶圆连接。 电子封装在接合焊盘区域和有源电路区域之间配备有边缘密封，并且包括裂缝停止件，其适于保护布置免受有害水分和组合进入含有 接合垫

公开(公告)号：US07205591B2

公开(公告)日：2007-04-17

申请号：US10907570

申请日：2005-04-06

Applicant: James W. Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Jerome B Lasky ,  Richard A. Phelps

Inventor： James W. Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Jerome B Lasky ,  Richard A. Phelps

IPC: H01L27/148

CPC classification number: H01L27/14689 ,  H01L27/14603 ,  H01L27/14609 ,  H01L31/0352

Abstract: A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.

Abstract translation: 像素传感器单元结构及其制造方法。 像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。 减少了由钉扎层引起的对电荷转移的电势障碍干扰。

公开(公告)号：US07098067B2

公开(公告)日：2006-08-29

申请号：US10905043

申请日：2004-12-13

Applicant: James W. Adkisson ,  Mark D. Jaffe ,  Arthur P. Johnson ,  Robert K. Leidy ,  Jeffrey C. Maling

Inventor： James W. Adkisson ,  Mark D. Jaffe ,  Arthur P. Johnson ,  Robert K. Leidy ,  Jeffrey C. Maling

IPC: H01L21/00

CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14687 ,  H01L27/14689

Abstract: A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a dopant region comprising material of the first conductivity type formed along a sidewall of the isolation region that is adapted to electrically couple the pinning layer to the substrate. The corresponding method facilitates an angled ion implantation of dopant material in the isolation region sidewall by first fabricating the photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material. To facilitate the angled implant to the sidewall edge past resist block masks, two methods are proposed: 1) a spacer type etch of the imaged photoresist; or, 2) a corner sputter process of the imaged photoresist.

Abstract translation: 形成在第一导电类型的衬底上的新型图像传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。 在光敏器件钉扎层附近形成沟槽隔离区。 该结构包括掺杂区域，该掺杂剂区域包括沿着隔离区域的侧壁形成的第一导电类型的材料，其适于将钉扎层电耦合到衬底。 相应的方法通过首先制造光致抗蚀剂层并且通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来促进掺杂剂材料在隔离区域侧壁中的成角度的离子注入。 为了促进通过抗蚀剂阻挡掩模的侧壁边缘的成角度注入，提出了两种方法：1）成像光致抗蚀剂的间隔物型蚀刻; 或2）成像光致抗蚀剂的角溅射工艺。

公开(公告)号：US06870225B2

公开(公告)日：2005-03-22

申请号：US09682957

申请日：2001-11-02

Applicant: Andres Bryant ,  Mark D. Jaffe

Inventor： Andres Bryant ,  Mark D. Jaffe

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795

Abstract: An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

Abstract translation: 一种改进的晶体管结构，可在不增加栅极至S / D电容的情况下降低源/漏（S / D）电阻，从而增加器件工作。 S / D结构通过半导体层形成在半导体晶片上形成的凹槽和具有至少两层的埋入式绝缘体的第一层。 由位于凹部之间的半导体层形成主体，并且主体包括限定主体厚度的顶部主体表面和底部主体表面。 S / D结构的顶部在体厚之内并与之相邻。 还描述了用于形成改进的晶体管结构的改进方法，并且包括：通过半导体层和埋入绝缘体的第一层形成凹槽，使得主体位于凹部之间; 并且将S / D结构形成到凹部中，使得S / D结构的顶部部分在主体厚度之内并且抵接在本体的厚度上。

公开(公告)号：US06394638B1

公开(公告)日：2002-05-28

申请号：US09560212

申请日：2000-04-28

Applicant: Edward W. Sengle ,  Mark D. Jaffe ,  Daniel Nelson Maynard ,  Mark Alan Lavin ,  Eric Jeffrey White ,  John A. Bracchitta

Inventor： Edward W. Sengle ,  Mark D. Jaffe ,  Daniel Nelson Maynard ,  Mark Alan Lavin ,  Eric Jeffrey White ,  John A. Bracchitta

IPC: H01L21762

CPC classification number: H01L21/76224 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

Abstract translation: 提供了一种用于半导体的沟槽隔离结构，包括隔离环和隔离路径。 隔离环围绕有源半导体区域，并且在非活性半导体区域的外部界定。 隔离通道从隔离环延伸穿过非活性半导体区域。 隔离路径上的第一级导体将有源半导体区域中的器件电连接或电容耦合到隔离环外部的衬底上的位置。 隔离路径具有从导体的布局导出的配置。