公开(公告)号：US20180219017A1

公开(公告)日：2018-08-02

申请号：US15422307

申请日：2017-02-01

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Yushi Hu

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/8234

Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced form the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US10026480B2

公开(公告)日：2018-07-17

申请号：US15669311

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  G11C11/56 ,  H01L27/105 ,  G11C16/34

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US09991273B2

公开(公告)日：2018-06-05

申请号：US15691477

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/1156 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11578

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

公开(公告)号：US09881686B2

公开(公告)日：2018-01-30

申请号：US15393719

申请日：2016-12-29

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US20170358359A1

公开(公告)日：2017-12-14

申请号：US15686510

申请日：2017-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yijie Zhao ,  Akira Goda

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/12 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3454

Abstract: Methods of programming a memory include applying a programming voltage on an access line selected for a programming operation of a single page of the memory, applying a second voltage on an access line unselected for the programming operation, increasing the programming voltage for a first plurality of steps of the programming operation, and increasing the second voltage for a second plurality of steps of a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.

公开(公告)号：US09679778B2

公开(公告)日：2017-06-13

申请号：US15154467

申请日：2016-05-13

Applicant: Micron Technology, Inc.

Inventor： Minsoo Lee ,  Akira Goda

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/764 ,  H01L29/788 ,  H01L29/423 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7889

Abstract: Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

公开(公告)号：US09633719B2

公开(公告)日：2017-04-25

申请号：US14724945

申请日：2015-05-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5622

Abstract: Embodiments of methods and memory devices for performing the methods are disclosed. In an embodiment, one such method includes programming all memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level and respectively programming all the memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.

公开(公告)号：US20170110198A1

公开(公告)日：2017-04-20

申请号：US15393719

申请日：2016-12-29

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US09576667B2

公开(公告)日：2017-02-21

申请号：US14538477

申请日：2014-11-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Goda ,  William C Filipiak

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  G11C2216/16

Abstract: Apparatuses and methods for a non-volatile memory scheme are described herein. An example apparatus may include a memory block including a plurality of subblocks of memory cells and further may include a control unit. The control unit may be configured to program a first access line group of each subblock of the plurality of subblocks during a program operation and to program a second access line group of each subblock of the plurality of subblocks during the program operation responsive to programming the first access line group of each of the plurality of subblocks.

Abstract translation: 本文描述了用于非易失性存储器方案的装置和方法。 示例性装置可以包括包括存储器单元的多个子块的存储块，并且还可以包括控制单元。 控制单元可以被配置为在编程操作期间对多个子块的每个子块的第一接入线组进行编程，并且在编程操作期间对多个子块的每个子块的第二接入线组进行编程， 多个子块中的每一个的访问线路组。

公开(公告)号：US20160372556A1

公开(公告)日：2016-12-22

申请号：US15255402

申请日：2016-09-02

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

IPC: H01L29/40 ,  H01L27/115

CPC classification number: H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.