公开(公告)号：US12176052B2

公开(公告)日：2024-12-24

申请号：US17969269

申请日：2022-10-19

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C7/06 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/42 ,  G11C29/44

Abstract: Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.

公开(公告)号：US20240274183A1

公开(公告)日：2024-08-15

申请号：US18582185

申请日：2024-02-20

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4093

CPC classification number: G11C11/4082 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4093

Abstract: Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.

公开(公告)号：US20240242758A1

公开(公告)日：2024-07-18

申请号：US18421741

申请日：2024-01-24

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Stefan Frederik Schippers

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4091 ,  H10B12/00 ,  G11C11/56

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4091 ,  H10B12/30 ,  H10B12/50 ,  G11C11/4087 ,  G11C11/565

Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.

公开(公告)号：US20240203490A1

公开(公告)日：2024-06-20

申请号：US18590692

申请日：2024-02-28

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Pierguido Garofalo ,  Umberto Di Vincenzo ,  Claudia Palattella

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C2013/0054

Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

公开(公告)号：US11996139B2

公开(公告)日：2024-05-28

申请号：US17611253

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C11/4096 ,  G11C11/404

CPC classification number: G11C11/4096 ,  G11C11/4045

Abstract: The present disclosure describes a memory device comprising memory cells at cross points of access lines of a memory array, and a two-transistor driver comprising a P-type transistor and a N-type transistor connected to the P-type transistor, the two-transistor driver being configured to drive an access line of the memory array to a discharging voltage during an IDLE phase, to drive said access line to a floating voltage during an ACTIVE phase, and to drive said access line at least to a first or second read/program voltage during a PULSE phase.

公开(公告)号：US11880571B2

公开(公告)日：2024-01-23

申请号：US17044150

申请日：2020-05-13

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto di Vincenzo

IPC: G06F3/06

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0653 ,  G06F3/0679

Abstract: The present disclosure relates to a method for accessing an array of memory cells, comprising the steps of storing user data in a plurality of memory cells of a memory array, storing, in a counter associated to the array of memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data stored in the array of memory cells, applying the read voltage to the cells of the counter to read the count data stored in the counter and to provide a target value corresponding to the number of bits in the user data having the first logic value, wherein, during the application of the read voltage, the count data are read simultaneously to the user data in such a way that the target value is provided during the reading of the user data, and based on the target value of the counter, stopping the application of the read voltage when the number of bits in the user data having the first logic value corresponds to the target value. A related memory device and a related system are also disclosed.

公开(公告)号：US11869587B2

公开(公告)日：2024-01-09

申请号：US17495423

申请日：2021-10-06

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

IPC: G11C13/00 ,  G11C16/04 ,  G11C7/10 ,  G11C16/28 ,  G11C11/22 ,  G11C7/14

CPC classification number: G11C13/004 ,  G11C7/1051 ,  G11C11/2255 ,  G11C11/2273 ,  G11C16/0483 ,  G11C16/28 ,  G11C7/14 ,  G11C2013/0054

Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.

公开(公告)号：US11862226B2

公开(公告)日：2024-01-02

申请号：US17463152

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera ,  Yen Chun Lee ,  Ferdinando Bedeschi

IPC: G11C11/4074 ,  G11C7/10 ,  G11C11/4096

CPC classification number: G11C11/4074 ,  G11C7/1063 ,  G11C7/1069 ,  G11C11/4096

Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a plurality of read voltages to the memory array based on the read request. The control circuit is further configured to perform a data analysis for a first set of data read based on the application of the plurality of read voltages and to derive a demarcation bias voltage (VDM) based on the data analysis. The control circuit is also configured to apply the VDM to the memory array to read a second set of data.

公开(公告)号：US20230335191A1

公开(公告)日：2023-10-19

申请号：US17720957

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Pierguido Garofalo ,  Umberto Di Vincenzo ,  Claudia Palattella

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C2013/0054

Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

公开(公告)号：US11756601B2

公开(公告)日：2023-09-12

申请号：US17499322

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221

Abstract: Methods, systems, and devices for differential sensing for a memory device are described. A memory device in accordance with examples as disclosed herein may include a sense component having a signal development component for generating a sense signal, a reference component for generating a reference signal, and a tail component coupled with the signal development component and the reference component. The tail component may be configured for canceling common aspects of the sense signal and the reference signal. Additionally or alternatively, a memory device in accordance with examples as disclosed herein may include a sense component having a sense amplifier configured to operate in multiple power domains, with one power domain associated with sense signal and reference signal generation and comparison, and another power domain associated with logical signal or information transfer.