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公开(公告)号:US09106224B2
公开(公告)日:2015-08-11
申请号:US14250623
申请日:2014-04-11
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Atsushi Umezaki
IPC: G05F1/10 , H03K17/081 , G09G3/20 , G11C19/18 , G11C19/28 , H03K19/0185
CPC classification number: H01L27/1255 , G02F1/1368 , G02F1/167 , G09G3/20 , G09G3/3225 , G09G3/344 , G09G3/3648 , G09G3/3688 , G09G2300/0426 , G09G2300/0819 , G09G2300/0876 , G09G2310/0286 , G09G2320/043 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/1225 , H01L27/124 , H01L27/3244 , H01L29/7869 , H03K3/356 , H03K17/08104 , H03K19/018521
Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.
Abstract translation: 提供了即使在其晶体管是耗尽晶体管的情况下也能够稳定地工作的半导体器件。 半导体器件包括用于向第一布线提供第一电位的第一晶体管,向第一布线提供第二电位的第二晶体管,提供第一晶体管导通的第三电位的第三晶体管, 第一晶体管并且停止提供第三电位,用于将第二电位提供给第一晶体管的栅极的第四晶体管和用于产生通过抵消第一信号而获得的第二信号的第一电路。 第二信号被输入到第四晶体管的栅极。 低电平的第二信号的电位低于第二电位。
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公开(公告)号:US20150123716A1
公开(公告)日:2015-05-07
申请号:US14594256
申请日:2015-01-12
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Atsushi Umezaki
IPC: H03K17/687 , G09G3/36 , G09G3/32
CPC classification number: H01L27/1255 , G09G3/14 , G09G3/32 , G09G3/36 , G09G2300/0426 , G09G2310/0286 , G09G2330/021 , G11C19/00 , H01L29/7869 , H03B1/00 , H03K3/00 , H03K17/6871
Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.
Abstract translation: 提供一种半导体器件,其特征在于晶体管数量减少的逆变器电路和移位寄存器电路。 半导体器件包括第一晶体管,第二晶体管和电容器。 第一晶体管的源极和漏极之一电连接到第一布线,另一个电连接到第二布线。 第二晶体管的源极和漏极之一电连接到第一布线,第二晶体管的栅极电连接到第一晶体管的栅极,第二晶体管的源极和漏极的另一个是 电连接到电容器的一个电极,而电容器的另一个电极电连接到第三布线。 第一和第二晶体管具有相同的导电类型。
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公开(公告)号:US08994028B2
公开(公告)日:2015-03-31
申请号:US14072878
申请日:2013-11-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Atsushi Umezaki
IPC: G09G3/36 , H01L27/105 , G11C19/28 , H01L27/12 , G02F1/1362 , H01L27/13 , H01L29/423 , H01L29/786
Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.
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公开(公告)号:US08952388B2
公开(公告)日:2015-02-10
申请号:US14072878
申请日:2013-11-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Atsushi Umezaki
IPC: G09G3/36 , H01L27/105 , G11C19/28 , H01L27/12 , G02F1/1362 , H01L27/13 , H01L29/423 , H01L29/786
Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.
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公开(公告)号:US08908115B2
公开(公告)日:2014-12-09
申请号:US13974328
申请日:2013-08-23
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Atsushi Umezaki , Hiroyuki Miyake
IPC: G02F1/136 , G02F1/1343 , G09G3/36 , G09G3/32 , H01L27/12 , H01L27/15 , G09G3/34 , H01L29/423 , G09G3/20
CPC classification number: G02F1/1368 , G02F1/136286 , G09G3/20 , G09G3/2022 , G09G3/3233 , G09G3/3266 , G09G3/3275 , G09G3/342 , G09G3/3426 , G09G3/3677 , G09G3/3685 , G09G2300/043 , G09G2300/0852 , G09G2310/0248 , G09G2310/0262 , G09G2310/027 , G09G2310/0275 , G09G2310/0286 , G09G2310/0297 , G09G2320/0233 , G09G2320/043 , G09G2330/021 , G09G2340/02 , G09G2352/00 , H01L27/12 , H01L27/1214 , H01L27/1222 , H01L27/124 , H01L27/1251 , H01L27/1255 , H01L27/156 , H01L27/3232 , H01L27/3276 , H01L29/42384 , H01L2924/0002 , H01L2924/00
Abstract: An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.
Abstract translation: 本发明的目的是提供一种能够降低显示装置的功耗和高清晰度的电路技术。 将由启动信号控制的开关提供给晶体管的栅电极,该晶体管连接到自举晶体管的栅电极。 当输入起始信号时,通过开关将电位提供给晶体管的栅电极,晶体管截止。 晶体管截止,从而可以防止电荷从自举晶体管的栅电极泄漏。 因此,可以缩短在自举晶体管的栅电极中存储电荷的时间,并且可以执行高速操作。
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公开(公告)号:US08860462B2
公开(公告)日:2014-10-14
申请号:US13675066
申请日:2012-11-13
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Atsushi Umezaki
IPC: H03K19/0175
Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.
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公开(公告)号:US20140299875A1
公开(公告)日:2014-10-09
申请号:US14295394
申请日:2014-06-04
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Atsushi Umezaki
IPC: H01L27/12
CPC classification number: H01L27/1251 , G09G3/325 , G09G2300/0408 , G09G2300/0819 , G09G2300/0852 , G09G2300/0861 , G09G2310/027 , G09G2310/0272 , H01L27/12 , H01L27/1214 , H01L27/1222 , H01L27/1225 , H01L27/1255 , H01L27/3244 , H01L27/3248 , H01L27/3262 , H01L27/3265
Abstract: A first capacitor obtains a gate-source voltage of a first transistor in accordance with a programming current flowing through the first transistor, and a second capacitor obtains a threshold voltage of a second transistor. Then, the electric charges held in the first capacitor and the second capacitor are capacitively coupled. By using the voltage obtained with the capacitively coupling as a gate-source voltage of the first transistor, constant current in accordance with the programming current can be supplied to a light emitting element.
Abstract translation: 第一电容器根据流过第一晶体管的编程电流获得第一晶体管的栅极 - 源极电压,并且第二电容器获得第二晶体管的阈值电压。 然后,保持在第一电容器和第二电容器中的电荷电容耦合。 通过使用通过电容耦合获得的电压作为第一晶体管的栅极 - 源极电压,可以向发光元件提供根据编程电流的恒定电流。
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公开(公告)号:US20140247070A1
公开(公告)日:2014-09-04
申请号:US14250623
申请日:2014-04-11
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Atsushi Umezaki
IPC: H03K17/081
CPC classification number: H01L27/1255 , G02F1/1368 , G02F1/167 , G09G3/20 , G09G3/3225 , G09G3/344 , G09G3/3648 , G09G3/3688 , G09G2300/0426 , G09G2300/0819 , G09G2300/0876 , G09G2310/0286 , G09G2320/043 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/1225 , H01L27/124 , H01L27/3244 , H01L29/7869 , H03K3/356 , H03K17/08104 , H03K19/018521
Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.
Abstract translation: 提供了即使在其晶体管是耗尽晶体管的情况下也能够稳定地工作的半导体器件。 半导体器件包括用于向第一布线提供第一电位的第一晶体管,向第一布线提供第二电位的第二晶体管,提供第一晶体管导通的第三电位的第三晶体管, 第一晶体管并且停止提供第三电位,用于将第二电位提供给第一晶体管的栅极的第四晶体管和用于产生通过抵消第一信号而获得的第二信号的第一电路。 第二信号被输入到第四晶体管的栅极。 低电平的第二信号的电位低于第二电位。
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公开(公告)号:US20140145187A1
公开(公告)日:2014-05-29
申请号:US14168058
申请日:2014-01-30
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Atsushi Umezaki
IPC: H01L27/12
CPC classification number: G02F1/136286 , G02F1/13306 , G02F1/133753 , G02F1/13452 , G02F1/136213 , G02F1/1368 , G02F1/1393 , G02F2001/133622 , G02F2202/103 , G09G3/342 , G09G3/3655 , G09G3/3674 , G09G3/3677 , G09G3/3685 , G09G2300/0426 , G09G2300/0452 , G09G2310/024 , G09G2310/0286 , G09G2310/08 , G09G2320/0252 , G09G2330/021 , G11C19/28 , H01L21/67167 , H01L27/06 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L27/15 , H01L27/156 , H01L27/3211 , H01L27/3213 , H01L27/3216 , H01L27/3248 , H01L27/3258 , H01L27/3262 , H01L27/3265 , H01L27/3276 , H01L29/247 , H01L29/78693 , H01L51/5246 , H01L51/56 , H01L2251/5307 , H01L2251/5315 , H01L2251/5323
Abstract: A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.
Abstract translation: 提供第一晶体管,第二晶体管,第三晶体管,第四晶体管。 在第一晶体管中,第一端子电连接到第一布线; 第二端子电连接到第二晶体管的栅极端子; 栅极端子电连接到第五布线。 在第二晶体管中,第一端子电连接到第三布线; 第二端子电连接到第六布线。 在第三晶体管中,第一端子电连接到第二布线; 第二端子电连接到第二晶体管的栅极端子; 栅极端子电连接到第四布线。 在第四晶体管中,第一端子电连接到第二布线; 第二端子电连接到第六布线; 栅极端子连接到第四布线。
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公开(公告)号:US20140117351A1
公开(公告)日:2014-05-01
申请号:US14147647
申请日:2014-01-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Jun Koyama , Atsushi Umezaki
IPC: H01L27/12
CPC classification number: G09G3/3677 , G09G2310/0251 , G09G2310/0286 , G09G2310/0289 , G09G2330/021 , G11C19/00 , H01L27/0207 , H01L27/1225 , H01L27/124 , H01L29/7869 , H03K17/687 , H03K19/0013 , H03K19/018557 , H03K19/018571
Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.
Abstract translation: 可以增加输入到电平移位器的信号的幅度电压,然后由电平移位器电路输出。 具体地,可以增加输入到电平移位器的信号的幅度电压以输出。 这降低了将输入到电平移位器的信号输出的电路(移位寄存器电路,解码器电路等)的振幅电压。 因此,可以降低电路的功耗。 或者,可以减小施加到电路中包括的晶体管的电压。 这可以抑制晶体管的劣化或对晶体管的损坏。
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