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    METHODS OF INCREASING SPACE FOR CONTACT ELEMENTS BY USING A SACRIFICIAL LINER AND THE RESULTING DEVICE
    111.
    发明申请
    METHODS OF INCREASING SPACE FOR CONTACT ELEMENTS BY USING A SACRIFICIAL LINER AND THE RESULTING DEVICE 有权
    通过使用真实内衬和结果设备来增加接触元件空间的方法

    公开(公告)号：US20140264479A1

    公开(公告)日：2014-09-18

    申请号：US13797001

    申请日：2013-03-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

    IPC: H01L29/40 ,  H01L29/417

    CPC classification number: H01L29/401 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636

    Abstract: One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least portions of the second liner layer relative to the first liner layer, forming a second layer of insulating material above the first layer of insulating material, performing at least one second etching process to remove at least portions of the first and second layers of insulating material and at least portions of the first liner layer so as to thereby expose an outer surface of the sidewall spacer, and forming a conductive contact that contacts the exposed outer surface of the sidewall spacer and a source/drain region of the transistor.

    Abstract translation: 一种方法包括在栅极结构附近形成侧壁间隔物，在侧壁间隔物上形成第一衬里层，在第一衬里层上形成第二衬里层，在衬底上方形成第一绝缘材料层并邻近第二衬层， 选择性地去除所述第二衬层的至少部分相对于所述第一衬层，在所述第一绝缘材料层之上形成第二绝缘材料层，执行至少一个第二蚀刻工艺以移除所述第一层和所述第二层的至少一部分 的绝缘材料和第一衬里层的至少部分，从而暴露侧壁间隔件的外表面，并且形成接触暴露的侧壁间隔物的外表面和晶体管的源极/漏极区域的导电接触。

    METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES
    112.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES 有权
    形成具有自对准接触元件和结果器件的半导体器件的方法

    公开(公告)号：US20140252424A1

    公开(公告)日：2014-09-11

    申请号：US13785403

    申请日：2013-03-05

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  John A. Iacoponi

    IPC: H01L21/768 ,  H01L23/48 ,  H01L29/40

    CPC classification number: H01L29/401 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.

    Abstract translation: 一种方法公开了进行蚀刻工艺以在源极/漏极区域的至少一部分上方的绝缘材料层中形成接触开口，其中在蚀刻工艺完成之后，晶体管的栅极结构的一部分是 暴露的，在暴露的栅极结构上选择性地形成可氧化材料，将可氧化材料的至少一部分转化为氧化物材料，以及在导电耦合到源/漏区的接触开口中形成导电接触。 本文公开的新型晶体管器件包括位于晶体管的导电接触和栅极结构之间的氧化物材料，其中氧化物材料接触导电接触并接触栅极结构的外表面的一部分但不全部接触。

    Prevention of fin erosion for semiconductor devices
    113.
    发明授权
    Prevention of fin erosion for semiconductor devices 有权
    防止半导体器件的翅片侵蚀

    公开(公告)号：US08809920B2

    公开(公告)日：2014-08-19

    申请号：US13670674

    申请日：2012-11-07

    Applicant: International Business Machines Corporation ,  GlobalFoundries Inc.

    Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L29/76

    CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

    Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

    INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE
    114.
    发明申请
    INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE 有权
    集成电路和方法制造集成电路，降低PARASIIC电容

    公开(公告)号：US20140138779A1

    公开(公告)日：2014-05-22

    申请号：US13682331

    申请日：2012-11-20

    Applicant: GLOBALFOUNDRIES, INC.

    Inventor： Ruilong Xie ,  Xiuyu Cai ,  Xunyuan Zhang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40

    CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/78

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成牺牲栅极结构。 在牺牲栅极结构周围形成间隔物，并且在间隔物和半导体衬底上沉积电介质材料。 该方法包括选择性地蚀刻间隔物以在牺牲栅极结构和电介质材料之间形成沟槽。 沟槽由沟槽表面限定，在该沟槽表面上沉积替代间隔物材料。 该方法合并替换间隔物材料的上部区域以在替换间隔物材料内包围空隙。

    METHODS OF FORMING 3-D SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND A NOVEL 3-D DEVICE
    115.
    发明申请
    METHODS OF FORMING 3-D SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND A NOVEL 3-D DEVICE 有权
    使用替代门技术和新颖的三维器件形成三维半导体器件的方法

    公开(公告)号：US20140084383A1

    公开(公告)日：2014-03-27

    申请号：US13628914

    申请日：2012-09-27

    Applicant: GLOBALFOUNDRIES INC,

    Inventor： Xiuyu Cai ,  Ruilong Xie

    IPC: H01L21/283 ,  H01L29/78 ,  H01L21/762

    CPC classification number: H01L29/0649 ,  H01L21/7624 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One illustrative method disclosed herein includes forming a sacrificial gate structure above a fin, wherein the sacrificial gate structure is comprised of a sacrificial gate insulation layer, a layer of insulating material, a sacrificial gate electrode layer and a gate cap layer, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin, and forming a replacement gate structure in the gate cavity. One illustrative device disclosed herein includes a plurality of fin structures that are separated by a trench formed in a substrate, a local isolation material positioned within the trench, a gate structure positioned around portions of the fin structures and above the local isolation material and an etch stop layer positioned between the gate structure and the local isolation material within the trench.

    Abstract translation: 本文公开的一种说明性方法包括在鳍片上形成牺牲栅极结构，其中牺牲栅极结构包括牺牲栅极绝缘层，绝缘材料层，牺牲栅电极层和栅极盖层，形成侧壁间隔物 牺牲栅极结构的相邻相对侧，去除牺牲栅极结构，从而限定露出翅片的一部分的栅极腔，并在栅极腔中形成替换栅极结构。 本文公开的一个示例性器件包括由形成在衬底中的沟槽分开的多个翅片结构，位于沟槽内的局部隔离材料，位于鳍结构的部分周围并位于局部隔离材料之上的栅结构，以及蚀刻 停止层位于沟槽内的栅极结构和局部隔离材料之间。

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