公开(公告)号：US20200243126A1

公开(公告)日：2020-07-30

申请号：US16261617

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal

IPC: G11C11/16 ,  G11C13/00

Abstract: A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.

公开(公告)号：US10726896B1

公开(公告)日：2020-07-28

申请号：US16261617

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00

Abstract: A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.

公开(公告)号：US10690845B1

公开(公告)日：2020-06-23

申请号：US16298354

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Abu Thomas ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/124 ,  G02B6/136 ,  H01L27/12 ,  G02B6/30

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to three dimensional (3D) optical interconnect structures and methods of manufacture. The structure includes: a first structure having a grating coupler and a first optical waveguide structure; and a second structure having a second optical waveguide structure in alignment with the first optical waveguide structure and which has a modal effective index that matches to the first optical waveguide structure.

公开(公告)号：US20200026000A1

公开(公告)日：2020-01-23

申请号：US16040896

申请日：2018-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136

Abstract: Structures including a waveguide arrangement and methods of fabricating a structure that includes a waveguide arrangement. A second waveguide spaced in a lateral direction from a first waveguide, a third waveguide spaced in a vertical direction from the first waveguide, and a fourth waveguide spaced in the vertical direction from the second waveguide. The third waveguide is arranged in the lateral direction to provide a first overlapping relationship with the first waveguide. The fourth waveguide is arranged in the lateral direction to provide a second overlapping relationship with the second waveguide.

公开(公告)号：US10468456B2

公开(公告)日：2019-11-05

申请号：US15898562

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jaiswal Akhilesh

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have complement magnetizations.

公开(公告)号：US10468083B1

公开(公告)日：2019-11-05

申请号：US16010841

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob

IPC: G11C5/06 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01L43/12 ,  H01L43/10

Abstract: Integrated circuits and methods of operating and producing the same are provided. In an exemplary embodiment, an integrated circuit includes a look up table with a first and second memory cell. The first memory cell includes a first magneto electric (ME) layer, a first free layer adjacent to the first ME layer, and a first fixed layer. The second memory cell includes a second ME layer, a second free layer adjacent to the second ME layer, and a second fixed layer. A first word line is in direct communication with the first and second free layers, wherein direct communication is a connection through zero, one, or more intervening components that are electrical conductors. A first bit line is in direct communication with the first ME layer, and a second bit line is in direct communication with the second ME layer.

公开(公告)号：US10461173B1

公开(公告)日：2019-10-29

申请号：US15990186

申请日：2018-05-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Xuan Anh Tran ,  Hui Zang ,  Bala Haran ,  Suryanarayana Kalaga

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234

Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.

公开(公告)号：US10185092B1

公开(公告)日：2019-01-22

申请号：US16032705

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/34 ,  G02B6/42 ,  G02B6/124

Abstract: Structures for grating couplers and methods of fabricating a structure including grating couplers. A first grating coupler includes a first plurality of grating structures. An interconnect structure includes a first metallization level that is positioned over the first grating coupler. A second grating coupler includes a second plurality of grating structures that are arranged in the first metallization level to overlap with the first grating coupler. The second plurality of grating structures are composed of a metal.

公开(公告)号：US20180233413A1

公开(公告)日：2018-08-16

申请号：US15950291

申请日：2018-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L21/823431 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/283 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: A FinFET device includes a fin formed in a semiconductor substrate, a gate structure positioned above a portion of the fin, and source and drain regions positioned on opposite sides of the gate structure, wherein the semiconductor substrate includes a first semiconductor material. A silicon-carbide (SiC) semiconductor material is positioned above the fin in the source region and the drain region, wherein the silicon-carbide (SiC) semiconductor material is different from the first semiconductor material. A graphene contact is positioned on and in direct physical contact with the silicon-carbide (SiC) semiconductor material in each of the source region and the drain region, and first and second contact structures are conductively coupled to the graphene contacts in the source region and the drain region, respectively.

公开(公告)号：US09864132B1

公开(公告)日：2018-01-09

申请号：US15282320

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Roderick A. Augur ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B6/12 ,  H01L23/373 ,  H01L27/092

CPC classification number: G02B6/12 ,  G02B2006/12061 ,  G02B2006/12135 ,  H01L23/373 ,  H01L23/3733 ,  H01L23/3738 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon waveguide devices in integrated photonics and methods of manufacture. The integrated photonics structure includes: a localized region of negative thermal expansion (NTE) coefficient material formed within a trench; at least one photonics or CMOS component contacting with the negative thermal expansion (NTE) coefficient material; and cladding material formed above the at least one photonics or CMOS component.