公开(公告)号：US09577033B2

公开(公告)日：2017-02-21

申请号：US14944450

申请日：2015-11-18

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L29/423 ,  H01L29/40 ,  H01L21/8234

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Abstract translation: 具有垂直漏极延伸MOS晶体管的半导体器件可以通过形成深沟槽结构以形成晶体管的垂直漂移区域而形成，使得每个垂直漂移区域通过深沟槽结构在至少两个相对侧上界定。 深沟槽结构被间隔开以形成漂移区域的RESURF区域。 在垂直漂移区域上的衬底中的沟槽中形成沟槽栅极。 身体区域位于垂直漂移区域上的衬底中。

公开(公告)号：US09553151B2

公开(公告)日：2017-01-24

申请号：US14731744

申请日：2015-06-05

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni ,  Jungwoo Joh

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L27/085

CPC classification number: H01L29/2003 ,  H01L27/085 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.

Abstract translation: 包含GaN FET的半导体器件具有在沟道区域外部的隔离栅极结构，其可操作以阻挡半导体器件的两个区域之间的二维电子气体中的电流。 隔离栅极结构与GaN FET的栅极同时形成，并且具有与栅极相同的结构。

公开(公告)号：US09553011B2

公开(公告)日：2017-01-24

申请号：US14101435

申请日：2013-12-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Eugen Mindricelu ,  Sameer Pendharkar ,  Seetharaman Sridhar

IPC: H01L27/088 ,  H01L21/761 ,  H01L27/02

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/0251

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

Abstract translation: 在包含具有第一导电类型的半导体材料的基板上形成集成电路。 在第一导电类型的半导体材料中形成具有第二相对导电类型的深阱。 通过深井在衬底中形成深的隔离沟槽，以将深井的未使用部分与深井的功能部分分开。 深井的功能部分包含集成电路的有源电路元件。 深井的分离部分不包含有源电路元件。 在深井的分离部分中形成具有第二导电类型和比深阱更高的平均掺杂密度的接触区域。 接触区域连接到集成电路的电压端子。

公开(公告)号：US09543149B2

公开(公告)日：2017-01-10

申请号：US14567398

申请日：2014-12-11

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland Hower ,  Sameer Pendharkar ,  Marie Denison

IPC: H01L27/105 ,  H01L29/66 ,  H01L21/225 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

Abstract translation: 一种集成电路和方法，其具有具有埋入漂移区域的扩展漏极MOS晶体管，在埋入漂移区域和漏极接触之间的漏极扩散连接，以及在埋入漂移区域和沟道之间同时形成的通道端扩散连接，其中 沟道末端扩散链路是通过分段区域注入形成的，以将掺杂稀释到漏极端扩散链路中的掺杂量的不到三分之二。

公开(公告)号：US20160300775A1

公开(公告)日：2016-10-13

申请号：US15183896

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Sameer Pendharkar

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/373

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

公开(公告)号：US20160276459A1

公开(公告)日：2016-09-22

申请号：US15168524

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Jacek Korec ,  John Manning Savidge Neilson ,  Sameer Pendharkar

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3205 ,  H01L29/739

CPC classification number: H01L29/66333 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32053 ,  H01L29/0834 ,  H01L29/7395

Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or grown epitaxial silicon for controlled drift region thickness and fast switching speed.

Abstract translation: 集成电路具有具有集成发射极短路的高压IGBT和使用晶片接合或生长的外延硅的制造工艺，用于控制漂移区厚度和快速开关速度。

公开(公告)号：US09431302B2

公开(公告)日：2016-08-30

申请号：US14712133

申请日：2015-05-14

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/265

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

公开(公告)号：US09397211B2

公开(公告)日：2016-07-19

申请号：US14559239

申请日：2014-12-03

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L21/324 ,  H01L21/225 ,  H01L21/761 ,  H01L21/266 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/0634 ,  H01L21/225 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

Abstract translation: 一种集成电路，其包含延伸漏极MOS晶体管，其具有漂移层，在上部RESURF层上并接触漂移层的上表面，以及在漂移层下面的埋入漏极延伸层，该漏极延伸层与漏极的漂移层电连接 在通道端处与漂移层分离。 可以在通道端处的漂移层和埋漏极延伸部之间形成较低的RESURF层。 上部RESURF层，漂移层，下部RESURF层和掩埋漏极延伸中的任何一个可以具有从漏极端到沟道端的渐变掺杂密度。 形成包含具有漂移层的延伸漏极MOS晶体管的集成电路的工艺，上部RESURF层和掩埋漏极延伸。

公开(公告)号：US09356117B2

公开(公告)日：2016-05-31

申请号：US14688639

申请日：2015-04-16

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L21/338 ,  H01L29/66 ,  H01L27/02 ,  H01L29/20 ,  H01L29/267 ,  H01L29/778 ,  H01L49/02 ,  H01L29/10 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/8232 ,  H01L29/201 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/7787 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7833

Abstract: A method for forming a semiconductor device including a GaN FET, an overvoltage clamping component, and a voltage dropping component. The GaN FET is formed by forming a low-defect layer comprising gallium nitride, a barrier layer comprising AlxGa1−xN, a gate, and source and drain contacts. The overvoltage clamping component is coupled to a drain node of the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node is less than a safe voltage limit and conducts significant current when the voltage rises above the safe voltage limit. The voltage dropping component is coupled to the overvoltage clamping component and to a terminal for a bias potential. The voltage dropping component provides a voltage drop which increases as current from the overvoltage clamping component increases. The GaN FET turns on when the voltage drop reaches a threshold value.

Abstract translation: 一种用于形成包括GaN FET，过压钳位部件和降压部件的半导体器件的方法。 通过形成包括氮化镓的低缺陷层，包含Al x Ga 1-x N的势垒层，栅极以及源极和漏极接触来形成GaN FET。 过电压钳位部件耦合到GaN FET的漏极节点。 当漏极节点处的电压小于安全电压极限时，过电压钳位元件导通无效电流，并在电压升高到安全电压极限以上时，导通大电流。 降压元件耦合到过电压钳位元件和与偏置电位的端子。 降压元件提供随着过电压钳位元件的电流增加而增加的电压降。 当电压降达到阈值时，GaN FET导通。

公开(公告)号：US20160079392A1

公开(公告)日：2016-03-17

申请号：US14949241

申请日：2015-11-23

Applicant: Texas Instruments Incorporated

Inventor： Philipp Steinmann ,  Amitava Chatterjee ,  Sameer Pendharkar

IPC: H01L29/66 ,  G06F17/50

CPC classification number: H01L29/66681 ,  G06F17/5081 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/861

Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

Abstract translation: 一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。 一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。 一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。