Method for forming semiconductor structure

    公开(公告)号:US11003084B2

    公开(公告)日:2021-05-11

    申请号:US16150789

    申请日:2018-10-03

    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The method includes exposing a portion of the resist layer by performing an exposure process. The resist layer includes a compound, and the compound has a carbon backbone, and a photoacid generator (PAG) group and/or a quencher group are bonded to the carbon backbone. The method also includes performing a baking process on the resist layer and etching a portion of the resist layer to form a patterned resist layer. The method includes patterning the material layer by using the patterned resist layer as a mask and removing the patterned resist layer.

    Material composition and methods thereof

    公开(公告)号:US10517179B2

    公开(公告)日:2019-12-24

    申请号:US15621646

    申请日:2017-06-13

    Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. In some examples, the patterned resist layer is coated with a treatment material. In some embodiments, the treatment material bonds to surfaces of the patterned resist layer to provide a treated patterned resist layer having a second pattern profile with a second proportion of active sites greater than the first proportion of active sites. By way of example, and as part of the coating the patterned resist layer with the treatment material, a first pattern shrinkage process may be performed, where the treated patterned resist layer has a second pattern width less than a first pattern width.

    Methods of reducing pattern roughness in semiconductor fabrication

    公开(公告)号:US10515812B1

    公开(公告)日:2019-12-24

    申请号:US16102347

    申请日:2018-08-13

    Abstract: A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution, and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant.

    Negative Tone Developer For Extreme Ultraviolet Lithography

    公开(公告)号:US20180341177A1

    公开(公告)日:2018-11-29

    申请号:US15694222

    申请日:2017-09-01

    CPC classification number: G03F7/325 G03F7/038 G03F7/16 G03F7/20 G03F7/2004

    Abstract: The present disclosure provides NTD developers and corresponding lithography techniques that can overcome resolution, line edge roughness (LER), and sensitivity (RLS) tradeoff barriers particular to extreme ultraviolet (EUV) technologies, thereby achieving high patterning fidelity for advanced technology nodes. An exemplary lithography method includes forming a negative tone resist layer over a workpiece; exposing the negative tone resist layer to EUV radiation; and removing an unexposed portion of the negative tone resist layer in a negative tone developer, thereby forming a patterned negative tone resist layer. The negative tone developer includes an organic solvent having a log P value greater than 1.82. The organic solvent is an ester acetate derivative represented by R1COOR2. R1 and R2 are hydrocarbon chains having four or less carbon atoms. In some implementations, R1, R2, or both R1 and R2 are propyl functional groups, such as n-propyl, isopropyl, or 2-methylpropyl.

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