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    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
    112.
    发明申请
    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200371937A1

    公开(公告)日：2020-11-26

    申请号：US16879264

    申请日：2020-05-20

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/0842 ,  G06F12/0888 ,  G06F12/0811

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    Multicore Bus Architecture With Wire Reduction and Physical Congestion Minimization Via Shared Transaction Channels
    119.
    发明申请
    Multicore Bus Architecture With Wire Reduction and Physical Congestion Minimization Via Shared Transaction Channels 审中-公开
    通过共享事务通道减少线路和物理拥塞最小化的多核总线架构

    公开(公告)号：US20160124890A1

    公开(公告)日：2016-05-05

    申请号：US14530266

    申请日：2014-10-31

    Applicant: Texas Instruments Incorporated

    Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

    IPC: G06F13/42 ,  G06F13/362

    CPC classification number: G06F13/4252 ,  G06F13/362

    Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

    Abstract translation: 多核总线架构（MBA）协议包括一种为所有事务类型共享相同物理通道的新技术。 使用两个通道，交易属性通道（TAC）和交易数据通道（TDC）。 属性信道发送可选地包括交易类型信号，交易ID，有效信号，总线代理ID信号，地址信号，交易大小信号，信用支出信号和信用回报信号的总线交易属性信息。 数据通道连接总线信号线的数据子集，与总线信号线的属性子集分开。 数据信道可选地发送数据有效信号，事务ID信号，总线代理ID信号和最后数据信号，以标记当前总线事务的最后数据。

    Multi processor bridge with mixed Endian mode support
    120.
    发明授权
    Multi processor bridge with mixed Endian mode support 有权
    具有混合端模式支持的多处理器桥

    公开(公告)号：US09304954B2

    公开(公告)日：2016-04-05

    申请号：US14031567

    申请日：2013-09-19

    Applicant: Texas Instruments Incorporated

    Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca

    IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G06F12/08

    CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the endian view used by each individual processor within the attached subsystem, and can perform the appropriate endian conversion on each processor's transactions to adapt the transaction to/from the endian view used by the interconnect.

    Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 异步网桥了解连接子系统内每个处理器使用的端点视图，并且可以对每个处理器的事务执行适当的端序转换，以使交易与互连使用的端点视图相适应。

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