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111.发明授权公开(公告)号：US08952451B2
公开(公告)日：2015-02-10
申请号：US14135588
申请日：2013-12-20
Applicant: United Microelectronics Corp.
Inventor： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yeng-Peng Wang , Chun-Hsien Lin , Chan-Lon Yang , Guang-Yaw Hwang , Shin-Chi Chen , Hung-Ling Shih , Jiunn-Hsiung Liao , Chia-Wen Liang
IPC: H01L29/66 , H01L29/78 , H01L21/8238
CPC classification number: H01L29/78 , H01L21/823842 , H01L21/82385 , H01L29/66545
Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.
Abstract translation: 具有金属栅极的半导体器件包括具有形成在其上的第一栅极沟槽和第二栅极沟槽的衬底，分别形成在第一栅极沟槽和第二栅极沟槽中的栅极电介质层，形成在栅极上的第一功函数金属层 第一栅极沟槽和第二栅极沟槽中的介电层，分别形成在第一栅极沟槽和第二栅极沟槽中的第二功函数金属层和形成在第二功函数金属层上的填充金属层。 第二栅极沟槽的开口宽度大于第一栅极沟槽的开口宽度。 第一栅极沟槽中的第二功函数金属层的上部区域比第一栅极沟槽中的第二功函数金属层的下部区域宽。
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公开(公告)号：US20150035069A1
公开(公告)日：2015-02-05
申请号：US13954991
申请日：2013-07-31
Applicant: United Microelectronics Corp.
Inventor： Yu-Hsiang Hung , Ssu-I Fu , Chien-Ting Lin , Po-Chao Tsao , Chung-Fu Chang , Cheng-Guo Chen
IPC: H01L27/092 , H01L21/8238
CPC classification number: H01L27/1211 , H01L21/845
Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.
Abstract translation: 公开了一种用于制造鳍状场效应晶体管（FinFET）的方法。 该方法包括以下步骤：提供衬底; 在基板中形成翅片状结构; 在衬底上并在鳍状结构的底部周围形成浅沟槽隔离（STI）; 在STI和鳍状结构上形成第一栅极结构; 以及去除STI的一部分以暴露在第一栅极结构下方的STI的侧壁。
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公开(公告)号：US20140302677A1
公开(公告)日：2014-10-09
申请号：US13859720
申请日：2013-04-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Ling Lin , Po-Chao Tsao , Chia-Jui Liang , Chien-Ting Lin
IPC: H01L21/311 , H01L21/3105
CPC classification number: H01L21/3086 , H01L21/823468 , H01L21/823864 , H01L29/66795
Abstract: A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.
Abstract translation: 一种用于制造半导体结构的方法，包括提供具有多个心轴图案和多个虚拟图案的基板，同时在心轴图案的侧壁上形成多个第一间隔件，在虚设图案的侧壁上形成多个第二间隔件，以及 移除第二间隔件和心轴图案以在基底上形成多个间隔图案。
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公开(公告)号：US20140273386A1
公开(公告)日：2014-09-18
申请号：US13802812
申请日：2013-03-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Chao Tsao , Chien-Ting Lin
IPC: H01L29/66
CPC classification number: H01L29/665 , H01L21/28247 , H01L21/28518 , H01L21/76814 , H01L21/76843 , H01L21/76897 , H01L21/823418 , H01L29/41783 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66628 , H01L29/7848
Abstract: A method of forming a metal silicide layer includes the following steps. At first, at least a gate structure, at least a source/drain region and a first dielectric layer are formed on a substrate, and the gate structure is aligned with the first dielectric layer. Subsequently, a cap layer covering the gate structure is formed, and the cap layer does not overlap the first dielectric layer and the source/drain region. Afterwards, the first dielectric layer is removed to expose the source/drain region, and a metal silicide layer totally covering the source/drain region is formed.
Abstract translation: 形成金属硅化物层的方法包括以下步骤。 首先，在基板上形成至少栅极结构，至少源极/漏极区域和第一电介质层，并且栅极结构与第一电介质层对准。 随后，形成覆盖栅极结构的覆盖层，并且覆盖层不与第一介电层和源极/漏极区重叠。 然后，去除第一电介质层以暴露源极/漏极区域，并且形成完全覆盖源极/漏极区域的金属硅化物层。
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公开(公告)号：US20140256136A1
公开(公告)日：2014-09-11
申请号：US13786485
申请日：2013-03-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Hung Tsai , Chun-Hsien Lin , Chien-Ting Lin
IPC: H01L21/308
CPC classification number: H01L21/3086 , H01L21/31053 , H01L21/76229 , H01L29/66795
Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a multiple-layer structure is formed on a substrate; then, a sacrificial pattern is formed on the multiple-layer structure, a spacer is formed on the sidewall of the sacrificial pattern and disposed on the multiple-layer structure, the sacrificial pattern is removed, the spacer is used as a cap layer to etch parts of the multiple-layer structure, and then the multiple-layer structure is used as a cap layer to etch the substrate and to form at least one fin structure in the substrate.
Abstract translation: 本发明提供一种形成翅片结构的方法，包括以下步骤：首先，在基板上形成多层结构; 那么，在多层结构上形成牺牲图案，在牺牲图案的侧壁上形成隔离物并且设置在多层结构上，去除牺牲图案，将间隔物用作盖层以蚀刻 多层结构的部分，然后多层结构用作覆盖层以蚀刻基底并在基底中形成至少一个翅片结构。
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Patent Agency Ranking
116.发明申请公开(公告)号：US20140252423A1
公开(公告)日：2014-09-11
申请号：US13784839
申请日：2013-03-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Chao Tsao , Chien-Ting Lin , Chien-Ming Lai , Chi-Mao Hsu
CPC classification number: H01L29/66545 , H01L21/28088 , H01L21/28185 , H01L21/32115 , H01L21/823842 , H01L27/0922 , H01L29/42364 , H01L29/42376 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/7833
Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.
Abstract translation: 具有金属栅极的半导体器件的制造方法包括以下步骤。 提供了具有形成在其上的第一半导体器件和第二半导体器件的衬底。 第一半导体器件包括第一栅极沟槽，第二半导体器件包括第二栅极沟槽。 第一功函数金属层形成在第一栅极沟槽和第二栅极沟槽中。 第一功函数金属层的一部分从第二栅极沟槽去除。 在第一栅极沟槽和第二栅极沟槽中形成第二功函数金属层。 第二功函数金属层和第一功函数金属层包括相同的金属材料。 在第一栅极沟槽和第二栅极沟槽中依次形成第三功函数金属层和间隙填充金属层。
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117.发明申请COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR, METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权补充金属氧化物半导体场效应晶体管，金属氧化物半导体场效应晶体管及其制造方法公开(公告)号：US20140191318A1
公开(公告)日：2014-07-10
申请号：US13738934
申请日：2013-01-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chien-Ting Lin , Shih-Hung Tsai
CPC classification number: H01L29/66598 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/0847 , H01L29/66636 , H01L29/66795 , H01L29/7833 , H01L29/7851
Abstract: A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is disposed on the substrate within a first transistor region and the second MOSFET is disposed on the substrate within a second transistor region. The first MOSFET includes a first fin structure, two first lightly-doped regions, two first doped regions and a first gate structure. The first fin structure includes a first body portion and two first epitaxial portions, wherein each of the first epitaxial portions is disposed on each side of the first body portion. A first vertical interface is between the first body portion and each of the first epitaxial portions so that the first-lightly doped region is able to be uniformly distributed on an entire surface of each first vertical interface.
Abstract translation: 互补金属氧化物半导体场效应晶体管（MOSFET）包括衬底，第一MOSFET和第二MOSFET。 第一MOSFET设置在第一晶体管区域内的衬底上，并且第二MOSFET设置在第二晶体管区域内的衬底上。 第一MOSFET包括第一鳍结构，两个第一轻掺杂区，两个第一掺杂区和第一栅结构。 第一翅片结构包括第一主体部分和两个第一外延部分，其中每个第一外延部分设置在第一主体部分的每一侧上。 第一垂直接口位于第一主体部分和第一外延部分之间，使得第一轻掺杂区域能够均匀分布在每个第一垂直界面的整个表面上。
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公开(公告)号：US12284812B2
公开(公告)日：2025-04-22
申请号：US18636306
申请日：2024-04-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.
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公开(公告)号：US20240032439A1
公开(公告)日：2024-01-25
申请号：US18373295
申请日：2023-09-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , JUN XIE
Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
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公开(公告)号：US11812669B2
公开(公告)日：2023-11-07
申请号：US17835986
申请日：2022-06-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , Jun Xie
Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
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