公开(公告)号：US20110042742A1

公开(公告)日：2011-02-24

申请号：US12917378

申请日：2010-11-01

申请人： Anup Bhalla ,  Dorman Pitzer ,  Jacek Korec ,  Xiaorong Shi ,  Sik Lui

发明人： Anup Bhalla ,  Dorman Pitzer ,  Jacek Korec ,  Xiaorong Shi ,  Sik Lui

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/8725 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

摘要翻译： 在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。 这避免了沟槽上角处的应力问题。 栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。 描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。 由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。

公开(公告)号：US20110042724A1

公开(公告)日：2011-02-24

申请号：US11634031

申请日：2009-04-20

申请人： Anup Bhalla ,  Sik K. Lui ,  Sung-Shan Tai

发明人： Anup Bhalla ,  Sik K. Lui ,  Sung-Shan Tai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L24/33 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming the sidewalls of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.

摘要翻译： 本发明公开了通过在半导体衬底的（110）晶体取向上形成沟槽的侧壁而制造的具有沟槽栅极的改进的MOSFET器件。 沟槽沿着沿着半导体衬底的不同晶体取向形成的沟槽的侧壁和底表面或沟槽的终端覆盖电介质氧化物层。 实施诸如氧化物退火工艺，特殊掩模或SOG工艺的特殊制造工艺以克服非均匀介电层生长的限制。

公开(公告)号：US20110037120A1

公开(公告)日：2011-02-17

申请号：US12583191

申请日：2009-08-14

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

摘要翻译： 半导体器件实施例包括衬底，衬底中的有源栅极沟槽和衬底中的不对称沟槽。 非对称沟槽具有第一沟槽壁和第二沟槽壁，第一沟槽壁衬有具有第一厚度的氧化物，并且第二沟槽壁衬有具有不同于第一厚度的第二厚度的氧化物。 另一半导体器件实施例包括衬底，衬底中的有源栅极沟槽; 以及衬底中的源极多晶硅拾取沟槽。 源多晶硅拾取沟槽包括多晶硅电极，并且多晶硅电极的顶表面在身体区域的底部之下。 另一个半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极，以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。 第二顶栅电极比第二底源电极窄。

公开(公告)号：US20100291744A1

公开(公告)日：2010-11-18

申请号：US12847863

申请日：2010-07-30

申请人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

发明人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/78

摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

摘要翻译： 沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。 在半导体基板的表面上形成硬掩模。 在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。 这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。 接下来将栅极沟槽掩模施加在硬掩模的顶部上。 栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。 栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。 第一种导电材料可以填充栅沟以形成栅极。 第二种导电材料可以填充身体接触沟槽以形成身体接触。

公开(公告)号：US07825431B2

公开(公告)日：2010-11-02

申请号：US12006398

申请日：2007-12-31

申请人： Anup Bhalla ,  Xiaobin Wang ,  Wei Wang ,  Yi Su ,  Daniel Ng

发明人： Anup Bhalla ,  Xiaobin Wang ,  Wei Wang ,  Yi Su ,  Daniel Ng

IPC分类号： H01L29/72 ,  H01L23/62

CPC分类号： H01L29/7811 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

摘要翻译： 支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。 该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。 在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件 钝化层。

公开(公告)号：US20100258897A1

公开(公告)日：2010-10-14

申请号：US12802790

申请日：2010-06-14

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/66727 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/782 ,  H01L29/8725

摘要： A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.

摘要翻译： 一种用于制造肖特基二极管的方法，包括以下步骤：1）提供具有与第一导电类型相反的第二导电类型的掺杂剂的区域，以在所述第一导电类型的半导体衬底中形成顶部掺杂区域; 2）通过顶部掺杂区域提供沟槽至预定深度并提供第二导电类型的掺杂剂以形成第二导电类型的底部掺杂区域; 以及3）将至少从顶部掺杂区域的底部延伸到底部掺杂区域的顶部的沟槽的侧壁上的肖特基势垒金属层衬里。

公开(公告)号：US07795108B2

公开(公告)日：2010-09-14

申请号：US12399632

申请日：2009-03-06

申请人： Tiesheng Li ,  Yu Wang ,  Yingying Lou ,  Anup Bhalla

发明人： Tiesheng Li ,  Yu Wang ,  Yingying Lou ,  Anup Bhalla

IPC分类号： H01L21/76

CPC分类号： H01L22/34 ,  H01L22/12 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut DL of the test structure is determined from the signal and an etch depth DT is determined from DL. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.

摘要翻译： 公开了一种用于确定深度蚀刻的方法，形成屏蔽栅沟槽（SGT）结构的方法和半导体器件晶片。 在具有沟槽的衬底的一部分上形成材料层。 材料填充沟槽。 将抗蚀剂掩模放置在材料层的测试部分上，从而限定位于抗蚀剂掩模下方的测试结构。 抗蚀剂掩模不覆盖沟槽。 该材料被各向同性地蚀刻并且测量与测试结构的电阻变化相关的信号。 从信号确定测试结构的横向底切DL，并且从DL确定蚀刻深度DT。 晶片可以包括形成桥接电路的一个或多个测试结构; 通过接触孔将测试结构电连接的一个或多个金属触点和包括在测试结构上的抗蚀剂层。

公开(公告)号：US20100200920A1

公开(公告)日：2010-08-12

申请号：US12378039

申请日：2009-02-09

申请人： Yi Su ,  Anup Bhalla ,  Daniel Ng

发明人： Yi Su ,  Anup Bhalla ,  Daniel Ng

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7815 ,  H01L29/8611 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.

摘要翻译： 一种半导体功率器件，其被支撑在半导体衬底上，该半导体衬底包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。 半导体还包括在栅极和漏极之间串联连接的栅极 - 漏极（GD）钳位端接器，还包括串联连接到硅二极管的多个背对背多晶硅二极管，包括半导体中的并行掺杂的列 衬底，其中平行掺杂的柱具有预定的间隙。 掺杂的柱还包括U形弯曲柱，其将平行掺杂的柱的端部连接在一起，深度掺杂的阱设置在U形弯曲部的下方并吞噬。

公开(公告)号：US07764105B2

公开(公告)日：2010-07-27

申请号：US12154948

申请日：2008-05-27

申请人： Anup Bhalla ,  Sik K. Lui

发明人： Anup Bhalla ,  Sik K. Lui

IPC分类号： H03K5/08

CPC分类号： H01L27/088 ,  H01L27/0629 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2223/6644 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48247 ,  H03K17/165 ,  H01L2924/00

摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

摘要翻译： 本发明公开了一种新的MOSFET器件。 MOSFET器件具有通过将低阻抗的并联FET连接到MOSFET器件而实现的改进的操作特性。 并联FET分流瞬态电流。 分流FET用于防止MOSFET器件无意中导通。 当在MOSFET器件的漏极处发生大的电压瞬变时，可能会发生MOSFET的无意开启。 通过将分流FET的栅极连接到MOSFET器件的漏极，在电路操作期间在正确的时间点提供低阻抗路径，以分流电流而不需要任何外部电路。

公开(公告)号：US20100163846A1

公开(公告)日：2010-07-01

申请号：US12319164

申请日：2008-12-31

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。